Patents by Inventor Ching-Wen Hung
Ching-Wen Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150228734Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.Type: ApplicationFiled: April 27, 2015Publication date: August 13, 2015Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
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Patent number: 9093285Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.Type: GrantFiled: March 22, 2013Date of Patent: July 28, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
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Publication number: 20150179457Abstract: A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.Type: ApplicationFiled: March 5, 2015Publication date: June 25, 2015Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Shih-Fang Tzou
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Patent number: 9064814Abstract: A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.Type: GrantFiled: June 19, 2013Date of Patent: June 23, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Ching Wu, Chih-Sen Huang, Ching-Wen Hung
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Patent number: 9064931Abstract: The present invention provides a semiconductor structure including at least a contact plug. The structure includes a substrate, a transistor, a first ILD layer, a second ILD layer and a first contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor and levels with a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The first contact plug is disposed in the first ILD layer and the second ILD layer and includes a first trench portion and a first via portion, wherein a boundary of the first trench portion and a first via portion is higher than the top surface of the gate. The present invention further provides a method of making the same.Type: GrantFiled: October 11, 2012Date of Patent: June 23, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
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Patent number: 9054172Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.Type: GrantFiled: December 5, 2012Date of Patent: June 9, 2015Assignee: UNITED MICROELECTRNICS CORP.Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
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Publication number: 20150145027Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Chih-Sen Huang, Jia-Rong Wu, Ching-Wen Hung
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Publication number: 20150118836Abstract: A method of fabricating a semiconductor device is disclosed. Provided is a substrate having a dummy gate formed thereon, a spacer on a sidewall of the dummy gate and a first dielectric layer surrounding the spacer. The dummy gate is removed to form a gate trench. A gate dielectric layer and at least one work function layer is formed in the gate trench. The work function layer and the gate dielectric layer are pulled down, and a portion of the spacer is laterally removed at the same time to widen a top portion of the gate trench. A low-resistivity metal layer is formed in a bottom portion of the gate trench. A hard mask layer is formed in the widened top portion of the gate trench.Type: ApplicationFiled: October 28, 2013Publication date: April 30, 2015Applicant: United Microelectronics Corp.Inventors: Ching-Ling Lin, Chih-Sen Huang, Jia-Rong Wu, Ching-Wen Hung, Po-Chao Tsao
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Publication number: 20150118835Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.Type: ApplicationFiled: October 25, 2013Publication date: April 30, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Chih-Sen Huang, Po-Chao Tsao, Ching-Wen Hung, Jia-Rong Wu, Chien-Ting Lin
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Publication number: 20150108553Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: ApplicationFiled: December 26, 2014Publication date: April 23, 2015Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Patent number: 9006804Abstract: A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.Type: GrantFiled: June 6, 2013Date of Patent: April 14, 2015Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Shih-Fang Tzou
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Patent number: 9006110Abstract: A method for fabricating a patterned structure of a semiconductor device includes: forming first mandrels and second mandrels on a substrate, wherein a first spacing is defined between the two adjacent first mandrels and a second spacing is defined between the two adjacent second mandrels, the first spacing being wider than the second spacing; forming a cover layer to cover the first mandrels while exposing the second mandrels; etching the cover layer and the second mandrels; removing the cover layer; concurrently forming first spacers on the sides of the first mandrels and a second spacers on the sides of the second mandrels after removing the cover layer; and transferring a layout of the first and second spacers to the substrate so as to form fin-shaped structures.Type: GrantFiled: November 8, 2013Date of Patent: April 14, 2015Assignee: United Microelectronics Corp.Inventors: Chien-Ying Sun, En-Chiuan Liou, Jia-Rong Wu, Ching-Wen Hung
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Patent number: 8993433Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.Type: GrantFiled: May 27, 2013Date of Patent: March 31, 2015Assignee: United Microelectronics Corp.Inventors: Chieh-Te Chen, Yu-Tsung Lai, Hsuan-Hsu Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung
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Patent number: 8962490Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon, wherein at least one metal gate is formed in the ILD layer and at least one source/drain region is adjacent to two sides of the metal gate; forming a first dielectric layer on the ILD layer; forming a second dielectric layer on the first dielectric layer; performing a first etching process to partially remove the second dielectric layer; utilizing a first cleaning agent for performing a first wet clean process; performing a second etching process to partially remove the first dielectric layer; and utilizing a second cleaning agent for performing a second wet clean process, wherein the first cleaning agent is different from the second cleaning agent.Type: GrantFiled: October 8, 2013Date of Patent: February 24, 2015Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, Jia-Rong Wu, Chih-Sen Huang, Chieh-Te Chen
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Patent number: 8951876Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.Type: GrantFiled: June 20, 2012Date of Patent: February 10, 2015Assignee: United Microelectronics Corp.Inventors: Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung
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Publication number: 20150008524Abstract: An integrated circuit device structure, in which, a diffusion region is formed in a substrate, an extension conductor structure is contacted with the diffusion region and extended externally to a position along a surface of the substrate, the position is outside the diffusion region, another extension conductor structure is contacted with the diffusion region, a jumper conductor structure is disposed over the substrate and on these two extension conductor structures for electrically connecting these two extension conductor structures, the jumper conductor structure may be over one or more gate structures, a contact structure penetrates through a dielectric layer to be contacted with the jumper conductor structure, and a metal conductor line is contacted with the contact structure.Type: ApplicationFiled: July 2, 2013Publication date: January 8, 2015Inventors: Ching-Wen Hung, Chih-Sen Huang
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Patent number: 8921226Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.Type: GrantFiled: January 14, 2013Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, En-Chiuan Liou, Chih-Sen Huang, Po-Chao Tsao
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Patent number: 8921947Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.Type: GrantFiled: June 10, 2013Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Ching Wu
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Publication number: 20140374805Abstract: A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Inventors: Yi-Ching Wu, Chih-Sen Huang, Ching-Wen Hung
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Publication number: 20140361352Abstract: A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.Type: ApplicationFiled: June 6, 2013Publication date: December 11, 2014Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Shih-Fang Tzou