Patents by Inventor Ching Yi

Ching Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240168206
    Abstract: A light scanning device comprises a rotatable polygon-shaped structure comprising a frame, a plurality of mirror bonding plates configured to reflect light, and one or more flexures. At least some mirror bonding plates of the plurality of mirror bonding plates are adjustably attached to the frame based on corresponding flexures of the one or more flexures. A plurality of adjustment mechanisms is inserted between the frame and corresponding mirror bonding plates of the plurality of mirror bonding plates, where the plurality of adjustment mechanisms is configured to adjust tilt angles of the corresponding mirror bonding plates.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 23, 2024
    Applicant: Innovusion, Inc.
    Inventors: Ching-Ling Meng, Ning-Yi Wang
  • Patent number: 11991479
    Abstract: The disclosure provides a time-lapse photographic device. The time-lapse photographic device includes a camera module, a drive module, an environment detection module, and a control unit. The drive module is connected to the camera module to drive the camera module to rotate. The environment detection module is configured to detect an external environment of the time-lapse photographic device to generate an environment detection signal. The control unit is electrically connected to the camera module, the drive module, and the environment detection module. The control unit generates, according to a shooting stop parameter, a plurality of intermittent drive signals to control the drive module, and controls the camera module to shoot at intervals of the drive signals. The control unit adjusts operation of at least one of the camera module and the drive module according to the environment detection signal.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: May 21, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Hsin-Yi Pu, Kai-Yu Hsu, Lai-Peng Wong, Chieh Li, Ting-Han Chang, Ching-Xsuan Chen
  • Patent number: 11980597
    Abstract: The disclosure provides methods for treating estrogen receptor positive (ER+) cancer in women with an effective amount of lasofoxifene, a pharmaceutically acceptable salt thereof, or a prodrug thereof. The disclosure also includes the detection of the Estrogen Receptor 1 (ESR1) gene mutations that lead to endocrine resistance and treatment of endocrine resistant ER+ cancers.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: May 14, 2024
    Assignee: Duke University
    Inventors: Kaitlyn Andreano, Ching-yi Chang, Donald P. McDonnell, Stephanie L. Gaillard
  • Patent number: 11981711
    Abstract: Provided herein are compositions, systems, kits, and methods for treating nervous system injuries caused by trauma or neurodegeneration or aging in a subject by administering a CSPG or SOCS3 reduction peptide (CRP and SRP respectively), or a nucleic acid sequence encoding the CRP or SRP, wherein both the CRP and SRP comprise a cell membrane penetrating domain, and a lysosome targeting domain, and the CRP further comprises a chondroitin sulfate proteoglycan (CSPG) binding domain, and the SRP further comprises a suppressor of cytokine signaling-3 (SOCS3) binding domain.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: May 14, 2024
    Assignee: The Cleveland Clinic Foundation
    Inventors: Yu-Shang Lee, Ching-Yi Lin
  • Publication number: 20240154215
    Abstract: An aluminum plastic film for a lithium battery and a method for manufacturing the same are provided. The method includes steps as follows: preparing a polyolefin adhesive; coating the polyolefin adhesive onto one surface of an aluminum foil layer; disposing an inner polyolefin layer onto the polyolefin adhesive; and drying the polyolefin adhesive, so that a polyolefin adhesive layer is formed between the aluminum foil layer and the inner polyolefin layer. Components of the polyolefin adhesive include a modified polyolefin polymer and a hardener. The modified polyolefin polymer has a modified group, a structure of the modified group contains maleic anhydride, and a molecular weight of the modified polyolefin polymer ranges from 100,000 g/mol to 200,000 g/mol.
    Type: Application
    Filed: February 17, 2023
    Publication date: May 9, 2024
    Inventors: TE-CHAO LIAO, SHIOU-YEH SHENG, TENG-KO MA, CHING-YAO YUAN, Chao-Hsien Lin, CHIA-YU LIN, YUN-BIN HSI, HAN-YI LEE, SHUN-CHIEH YANG
  • Patent number: 11978782
    Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11974983
    Abstract: The disclosure provides methods for treating estrogen receptor positive (ER+) cancer in women with an effective amount of lasofoxifene, a pharmaceutically acceptable salt thereof, or a prodrug thereof. The disclosure also includes the detection of the Estrogen Receptor 1 (ESR1) gene mutations that lead to endocrine resistance and treatment of endocrine resistant ER+ cancers.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: May 7, 2024
    Assignee: Duke University
    Inventors: Kaitlyn Andreano, Ching-yi Chang, Donald P. McDonnell, Stephanie L. Gaillard
  • Patent number: 11973958
    Abstract: Methods and apparatus of video coding using sub-block based affine mode are disclosed. According to this method, control-point motion vectors (MVs) associated with the affine mode are determined for a block. A sub-block MV is derived for a target sub-block of the block from the control-point MVs for the block. A prediction offset is determined for a target pixel of the target sub-block using information comprising a pixel MV offset from the sub-block MV for the target pixel according to Prediction Refinement with Optical Flow (PROF). The target pixel of the target sub-block is encoded or decoded using a modified predictor. The modified prediction is generated by clipping the prediction offset to a target range and combining the clipped prediction offset with an original predictor.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 30, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Zhi-Yi Lin
  • Publication number: 20240136227
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Publication number: 20240134044
    Abstract: A laser device for providing light to a LiDAR system comprises a plurality of seed lasers configured to provide multiple seed light beams, at least two of the seed light beams having different wavelengths. An amplifier is optically coupled to the plurality of seed lasers to receive the multiple seed light beams. A power pump is configured to provide pump power to the amplifier, where the amplifier amplifies the multiple seed light beams using the pump power to obtain amplified light beams. A second light coupling unit is configured to demultiplex the amplified light beams to obtain a plurality of output light beams, at least two of the output light beams having wavelengths corresponding to the wavelengths of the at least two seed light beams.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: Innovusion, Inc
    Inventors: Yufeng Li, Orkhongua Batjargal, Peng Wan, Yimin Li, Junwei Bao, Jia Ge, Yang Han, Ching-Ling Meng, Ning-Yi Wang
  • Patent number: 11967591
    Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee
  • Patent number: 11965069
    Abstract: A heat-shrinkable polyester film made of a polyester-forming resin composition includes a recycled material, and has an exothermic crystallization peak and an endothermic melting peak which are determined via differential scanning calorimetry, and which satisfy relationships of T2?T1?68° C. and T3?T2?78° C., where T1 represents an onset point of the exothermic crystallization peak, T2 represents an end point of the exothermic crystallization peak and an onset point of the endothermic melting peak, and T3 represents an end point of the endothermic melting peak. A method for manufacturing the heat-shrinkable polyester film is also disclosed.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: April 23, 2024
    Assignee: FAR EASTERN NEW CENTURY CORPORATION
    Inventors: Li-Ling Chang, Yow-An Leu, Ting-Yu Lin, Ching-Chun Tsai, Wen-Yi Chang
  • Publication number: 20240128313
    Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Tse-Hsiao LIU, Chih-Wei LIN, Po-Hao CHIU, Pi-Kuang CHUANG, Ching-Yi HSU
  • Publication number: 20240128381
    Abstract: A power diode device includes a substrate. The substrate includes a core layer of a first conductive type, a first diffusion layer of the first conductive type, a second diffusion layer of a second conductive type, and a heavily doped region of the second conductive type. The core layer is located between the first diffusion layer and the second diffusion layer. A thickness of the core layer is greater than that of the second diffusion layer. The heavily doped region is located in the second diffusion layer and extends toward the core layer to form a PN junction between the heavily doped region and the core layer. A method for manufacturing the power diode device is also provided.
    Type: Application
    Filed: June 2, 2023
    Publication date: April 18, 2024
    Inventors: Ching Chiu TSENG, Tzu Yuan LO, Chao Yi CHANG
  • Publication number: 20240126973
    Abstract: A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.
    Type: Application
    Filed: August 10, 2023
    Publication date: April 18, 2024
    Inventors: Ching Hsu, Heng-Yi Lin, Yi-Lin Chuang
  • Patent number: 11955707
    Abstract: An antenna module includes first to third radiators and a ground radiator. The first radiator includes first and second sections and excites at a first frequency band. An extension direction of the first section, including a feeding end, is not parallel to an extension direction of the second section. The second radiator includes third and fourth sections. The third section extends from an intersection of the first and second sections. The third section excites at a second frequency band. The third radiator is disposed beside the first radiator and away from the second radiator. The ground radiator is disposed on one side of the first, second, and third radiators, and includes a ground end. The fourth section of the second radiator is connected to the third section and the ground radiator. The third radiator is connected to the ground end.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: April 9, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Chao-Hsu Wu, Hau Yuen Tan, Chien-Yi Wu, Shih-Keng Huang, Cheng-Hsiung Wu, Ching-Hsiang Ko
  • Patent number: 11956972
    Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Si-Han Tsai, Ching-Hua Hsu, Chen-Yi Weng, Po-Kai Hsu
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Patent number: 11948837
    Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fu Yeh, Chin-Lung Chung, Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
  • Patent number: D1024126
    Type: Grant
    Filed: January 2, 2023
    Date of Patent: April 23, 2024
    Assignee: Acer Medical Inc.
    Inventor: Ching-Yi Chen