Patents by Inventor Ching Yi

Ching Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030455
    Abstract: A positive electrode and a battery employing the same encapsulant composition are provided. The positive electrode includes a positive electrode active layer and a first layer, wherein the first layer is disposed on the positive electrode active layer, and the first layer includes a lithium-iron-phosphorus-containing oxide and a first binder. The electric resistance ratio of the first layer to the positive electrode active layer is greater than or equal to 100.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 25, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Deng-Tswen SHIEH, Yu-Han LIN, Ching-Yi SU
  • Publication number: 20240027185
    Abstract: A method for measuring a thickness of a thin film layer disposed on a piece of glass is implemented using a computer device that stores a thin film image of the thin film layer, a surface dataset associated with a surface of the thin film layer, and a plurality of reference parameter sets each being associated with a specific thickness of the thin film layer, the method including: generating a spectral image dataset that includes spectral data associated with different pixels of the thin film image using a spectral transformation matrix; performing regression analysis on the surface dataset and the spectral image dataset, so as to obtain a thickness parameter set including a plurality of thickness parameters; and determining a thickness of the thin film layer using the thickness parameter set and the plurality of reference parameter sets.
    Type: Application
    Filed: October 27, 2022
    Publication date: January 25, 2024
    Applicant: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Yu-Yang Chen, Yu-Ming Tsao, Yu-Lin Liu, Ching-Yi Huang
  • Publication number: 20240020263
    Abstract: A chip includes a peripheral component interconnect express (PCIe) switch, a dual-mode device, and a signal transmission control circuit. The PCIe switch includes a first downstream port. The dual-mode device switches between a root complex (RC) mode and an endpoint (EP) mode. The signal transmission control circuit is coupled between the PCIe switch and the dual-mode device. The first downstream port communicates with the dual-mode device operating under the EP mode. The signal transmission control circuit allows an external PCIe device to communicate with the dual-mode device operating under the RC mode.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Applicant: MEDIATEK INC.
    Inventor: Ching-Yi Wu
  • Publication number: 20240021441
    Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 18, 2024
    Inventors: Ching-Yi Lin, Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen
  • Publication number: 20240005103
    Abstract: This disclosure provides a method and a user apparatus for generating and applying a translation marker, and the method is performed by the user apparatus and comprises: opening an electronic document on a user operation interface; selecting at least one text string in the electronic document according to a first triggering event; and when a translation option is detected to be selected, performing the following steps: generating a code corresponding to the selected text string by using an operation function; and displaying a first translated text string of the first translation record on the user operation interface and generating a first translation marker associated with the first translated text string on the electronic document when it is determined that a first translation record associated with the code exists in the user apparatus.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 4, 2024
    Inventors: YU-WEN CHEN, CHIA-TING LEE, WEN-WEI LIN, KAI-LIN SHIH, CHING-YI CHIANG
  • Publication number: 20240005408
    Abstract: A method for generating a tree diagram of a shareholding structure from a capitalization table of a company, includes: generating a plurality of interactive icons that include a root node icon associated with the company, and a plurality of stem node icons each associated with a respective one of a plurality of related-parties recorded in the capitalization table, each of the related-parties being a partial owner or a subsidiary party; arranging the root node icon at an origin of the tree diagram, and arranging the stem node icons in the tree diagram such that the stem node icons associated with partial owners are on one side of the tree diagram and the stem node icons associated with the subsidiary parties are on an opposite side of the tree diagram; and plotting a plurality of investment routes each connecting two interactive icons arranged in the tree diagram.
    Type: Application
    Filed: June 26, 2023
    Publication date: January 4, 2024
    Inventors: Bo-Ru LIN, Shang-De YOU, Hsien-Chun MENG, Ching-Yi WANG, San-Wen CHEN
  • Publication number: 20230390358
    Abstract: Disclosed herein is a method for alleviating depression, which includes administering to a subject in need thereof a composition containing TNFAIP3-interacting protein (TNIP) 1. The composition is administered to the CA3 region of the subject's hippocampus.
    Type: Application
    Filed: February 22, 2023
    Publication date: December 7, 2023
    Inventors: Yi-Yung Hung, Hong-Yo Kang, Ching-Yi Tsai, Ya-Ling Huang
  • Publication number: 20230395426
    Abstract: Provided is a conductive structure and a method for forming such a structure. The method includes forming a treatable layer by depositing a layer comprising a metal over a structure; performing a directional treatment process on a targeted portion of the treatable layer to convert the targeted portion to a material different from a non-targeted portion of the treatable layer, wherein the directional treatment process is selected from the group consisting of nitridation, oxidation, chlorination, carbonization; and selectively removing the non-targeted portion from the structure, wherein the targeted portion remains over the structure.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiang Chao, Shu-Lan Chang, Ching-Yi Chen, Shih-Wei Yeh, Pei Shan Chang, Ya-Yi Cheng, Yu-Chen Ko, Yu-Shiuan Wang, Chun-Hsien Huang, Hung-Chang Hsu, Chih-Wei Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20230387103
    Abstract: A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends in a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend in the first direction. The second and third well regions have a second conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shielding structure.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsien-Feng LIAO, Jian-Hsing LEE, Chieh-Yao CHUANG, Ting-Yu CHANG, Yeh-Ning JOU, Shao-Chang HUANG, Kan-Sen CHEN, Nai-Lun CHENG, Ching-Yi HSU, Yu-Chen WU
  • Publication number: 20230387078
    Abstract: A semiconductor device includes an integrated passive device coupled to a redistribution structure by a plurality of first bumps, and having a plurality of second bumps disposed opposite the plurality of first bumps, wherein the plurality of first and second bumps are thermally and/or electrically connected, and thus enable further thermal and/or electrical connections within or comprising the semiconductor device.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fong-yuan Chang, Ho Che Yu, Yu-Hao Chen, Yii-Chian Lu, Ching-Yi Lin, Jyh Chwen Frank Lee
  • Publication number: 20230366873
    Abstract: A system and method utilize capacitance sensor data to identify cell events with single-cell resolution. The method identifies patterns in the sensor data related to events such as mitosis, migration-in to the sensor field, and migration-out. The system may include a processor co-located with the sensor to perform the pattern recognition. Further, microfluidic channels can be provided to direct cells to the sensors.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 16, 2023
    Applicant: Carnegie Mellon University
    Inventors: Marc Peralte Dandin, Ching-Yi Lin
  • Patent number: 11817324
    Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Yi Lin, Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen
  • Publication number: 20230357477
    Abstract: The present application is a composition including abase resin comprising between about 4% and about 15% acrylic acid monomer and an oligomer additive comprising (a) one of an acrylamide or meth(acrylamide) copolymer and (b) a high glass transition temperature monomer. The oligomer additive has a molecular weight range of between about 20,000 and about 1,000,000 and a glass transition temperature of between about 70° C. and about 115° C. The composition has a blending ratio of base resin to oligomer additive of between about 7 to about 30 parts per hundred of resin.
    Type: Application
    Filed: October 5, 2021
    Publication date: November 9, 2023
    Inventors: Sung-Tso Lin, Ching-Yi Liu, Ying-Yuh Lu, Wei-Cheng Su
  • Publication number: 20230354556
    Abstract: A computing system including a water-resistant chassis, at least one electronic component with a heat sink, and a gap filler. The heat sink includes an arrangement of fins separated by inter-fin spaces. The gap filler is in contact with both the heat sink and the water-resistant chassis. The gap filler is positioned in the inter-fin spaces to provide a heat conduction path between the heat sink and the chassis.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Inventors: Yi-Chieh CHEN, Yueh-Chang WU, Ching-Yi SHIH, Kang HSU
  • Patent number: 11803503
    Abstract: A chip includes a peripheral component interconnect express (PCIe) switch, a dual-mode device, and a signal transmission control circuit. The PCIe switch includes a first downstream port. The dual-mode device switches between a root complex (RC) mode and an endpoint (EP) mode. The signal transmission control circuit is coupled between the PCIe switch and the dual-mode device. The first downstream port communicates with the dual-mode device operating under the EP mode. The signal transmission control circuit allows an external PCIe device to communicate with the dual-mode device operating under the RC mode.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: October 31, 2023
    Assignee: MEDIATEK INC.
    Inventor: Ching-Yi Wu
  • Publication number: 20230332841
    Abstract: A thermal ground plane (TGP) is disclosed. A TGP may include a first planar substrate member comprising copper and a second planar substrate member comprising a metal, wherein the first planar substrate member and the second planar substrate member enclose a working fluid. The TGP may include a first plurality of pillars disposed on an interior surface of the first planar substrate and a mesh layer disposed on the top of the first plurality of pillars, wherein the mesh layer comprises at least one of copper, polymer encapsulated with copper, or stainless steel encapsulated with copper. The TGP may also include a second plurality of pillars disposed on an interior surface of the second planar substrate member within an area defined by the perimeter of the second planar substrate member and the second plurality of pillars extend from the second planar substrate member to the mesh layer.
    Type: Application
    Filed: March 7, 2023
    Publication date: October 19, 2023
    Inventors: Ryan John Lewis, Li-Anne Liew, Ching-Yi Lin, Collin Jennings Coolidge, Shanshan Xu, Ronggui Yang, Yung-Cheng Lee
  • Patent number: 11792900
    Abstract: A dimmer circuit includes a light emitting module, a first current source, a digital-to-analog converter, a switch, a second current source and a pulse width modulation generator. The light emitting module is for emitting light according to a driving current. The first current source includes a first terminal coupled to a second terminal of the light emitting module. The digital-to-analog converter is for generating a DC voltage according to a DC dimming code signal to control the first current source. The switch includes a first terminal coupled to a second terminal of the light emitting module. The second current source includes a first terminal coupled to a second terminal of the switch. The PWM generator is for generating a PWM voltage according to the PWM dimming code signal to control the second current source.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: October 17, 2023
    Assignee: RICHTEK TECHNOLOGY CORP.
    Inventors: Ching-Yi Chen, Hsing-Shen Huang
  • Publication number: 20230307268
    Abstract: A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yung-Hsiang Chen, Yun-Chou Wei, Ke-Fang Hsu, Ching-Yi Hsu, Yen-Shih Ho
  • Publication number: 20230303644
    Abstract: Provided herein are compositions, systems, kits, and methods for treating nervous system injuries caused by trauma or neurodegeneration or aging in a subject by administering a CSPG or SOCS3 reduction peptide (CRP and SRP respectively), or a nucleic acid sequence encoding the CRP or SRP, wherein both the CRP and SRP comprise a cell membrane penetrating domain, and a lysosome targeting domain, and the CRP further comprises a chondroitin sulfate proteoglycan (CSPG) binding domain, and the SRP further comprises a suppressor of cytokine signaling-3 (SOCS3) binding domain.
    Type: Application
    Filed: January 25, 2023
    Publication date: September 28, 2023
    Inventors: Yu-Shang Lee, Ching-Yi Lin
  • Patent number: D1012943
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 30, 2024
    Assignee: Acer Medical Inc.
    Inventor: Ching-Yi Chen