Patents by Inventor Ching Yi

Ching Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11497730
    Abstract: The disclosure provides methods for treating estrogen receptor positive (ER+) cancer in women with an effective amount of lasofoxifene, a pharmaceutically acceptable salt thereof, or a prodrug thereof. The disclosure also includes the detection of the Estrogen Receptor 1 (ESR1) gene mutations that lead to endocrine resistance and treatment of endocrine resistant ER+ cancers.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: November 15, 2022
    Assignee: Duke University
    Inventors: Kaitlyn Andreano, Ching-yi Chang, Donald P. McDonnell, Stephanie L. Gaillard
  • Publication number: 20220328409
    Abstract: In some embodiments, a low-resistance path between an active cell and a power supply layer in an integrated circuit device includes at least one layer of a plurality of conductive lines commonly connected to at least one conductive line through a plurality of respective conductive pillars, the at least one conductive line being in the power supply layer or intervening the active cell and the power supply layer. In some embodiments, the integrated circuit device includes a conductive layer that includes the plurality of conductive lines and additional conductive portions, where the plurality of conductive lines are isolated from the additional conductive portions.
    Type: Application
    Filed: November 30, 2021
    Publication date: October 13, 2022
    Inventors: Ho-Che Yu, Fong-yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Chen-Yi Chang
  • Patent number: 11467403
    Abstract: An operating method of an electronic system is provided. The operating method of the electronic system includes generating a first user input by a first input device and performing a first input control according to the first user input during a first input operation mode, determining whether a light intersection point of a ray emitted by a second input device with a virtual reality (VR) environment exists in the VR environment, switching to a second input operation mode in response to determining that the light intersection point of the ray with the VR environment exists in the VR environment and generating a second user input by the second input device and performing a second input control according to the second user input during the second input operation mode.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: October 11, 2022
    Assignee: HTC Corporation
    Inventor: Ching-Yi Chang
  • Patent number: 11436992
    Abstract: A display system and a method for forming an output buffer of a source driver are provided. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver provides a plurality of gate signals to the plurality of gate lines. A source driver provides a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer includes a transistor. The transistor is either a native transistor device, a depletion-mode transistor device or a low-threshold transistor device.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 6, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Lung Chin, Ching-Yi Hsu, Chang-He Liu, Chih-Cherng Liao, Jun-Wei Chen, Leuh Fang
  • Publication number: 20220277997
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 1, 2022
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Patent number: 11387361
    Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: July 12, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chin-Hsiu Huang, Tse-Hsiao Liu, Pao-Hao Chiu, Chih-Cherng Liao, Ching-Yi Hsu
  • Publication number: 20220194762
    Abstract: A method and a system for controlling a handling machine, and a non-volatile computer readable recording medium are provided. The method includes: analyzing image data to obtain contour data corresponding to a target in the image data; analyzing the contour data to obtain feature data, where the feature data reflects the position of the target in the physical space; and generating control data based on the feature data, where the control data is adapted to control the handling machine to transport the target in response to the position of the target in the physical space.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Tsung-Ting Tsai, Carlos Andres Betancourt Baca, Yen-Chung Chang, Ching-Yi Liu
  • Patent number: 11342225
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Publication number: 20220136155
    Abstract: Aspects herein are directed to a composite nonwoven textile suitable for use in apparel and other articles that are resistant to pilling. The composite nonwoven textile may be finished by one or more of applying a chemical binder to a first face of the composite nonwoven textile and forming thermal bonding sites. The chemical binder and the thermal bonding sites help to secure fiber terminal ends and minimize the formation of pills.
    Type: Application
    Filed: October 26, 2021
    Publication date: May 5, 2022
    Inventor: Ching-Yi Chien
  • Publication number: 20220110445
    Abstract: A storage rack contains: a rectangular platform, two support feet, a rectangular plane, two long fringes, two short fringes, four circular orifices, four oval orifices, and two grips which. The two support feet are connected on the rectangular platform, and a respective support foot has a first inward bending portion and a second inward bending portion which are formed on two free ends of two tops of the respective support foot. Each of the first inward bending portion and the second inward bending portion has an arcuate face and an insertion, the arcuate face corresponds to a respective oval orifice of a respective long fringe of the rectangular platform, and the insertion corresponds to a respective circular orifice of the respective long fringe of the rectangular platform, such that the insertion is rotatably accommodated into the respective circular orifice to expand or retract the respective support foot freely.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 14, 2022
    Inventor: Ching-Yi CHEN
  • Patent number: 11278115
    Abstract: A storage rack contains: a rectangular platform, two support feet, a rectangular plane, two long fringes, two short fringes, four circular orifices, four oval orifices, and two grips which. The two support feet are connected on the rectangular platform, and a respective support foot has a first inward bending portion and a second inward bending portion which are formed on two free ends of two tops of the respective support foot. Each of the first inward bending portion and the second inward bending portion has an arcuate face and an insertion, the arcuate face corresponds to a respective oval orifice of a respective long fringe of the rectangular platform, and the insertion corresponds to a respective circular orifice of the respective long fringe of the rectangular platform, such that the insertion is rotatably accommodated into the respective circular orifice to expand or retract the respective support foot freely.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: March 22, 2022
    Inventor: Ching-Yi Chen
  • Publication number: 20220057634
    Abstract: An operating method of an electronic system is provided. The operating method of the electronic system includes generating a first user input by a first input device and performing a first input control according to the first user input during a first input operation mode, determining whether a light intersection point of a ray emitted by a second input device with a virtual reality (VR) environment exists in the VR environment, switching to a second input operation mode in response to determining that the light intersection point of the ray with the VR environment exists in the VR environment and generating a second user input by the second input device and performing a second input control according to the second user input during the second input operation mode.
    Type: Application
    Filed: August 20, 2020
    Publication date: February 24, 2022
    Inventor: Ching-Yi Chang
  • Publication number: 20220031658
    Abstract: The disclosure provides methods for treating estrogen receptor positive (ER+) cancer in women with an effective amount of lasofoxifene, a pharmaceutically acceptable salt thereof, or a prodrug thereof. The disclosure also includes the detection of the Estrogen Receptor 1 (ESR1) gene mutations that lead to endocrine resistance and treatment of endocrine resistant ER+ cancers.
    Type: Application
    Filed: April 9, 2018
    Publication date: February 3, 2022
    Inventors: Kaitlyn ANDREANO, Ching-yi CHANG, Donald P. McDONNELL, Stephanie L. GAILLARD
  • Publication number: 20210361596
    Abstract: The disclosure provides methods for treating estrogen receptor positive (ER+) cancer in women with an effective amount of lasofoxifene, a pharmaceutically acceptable salt thereof, or a prodrug thereof. The disclosure also includes the detection of the Estrogen Receptor 1 (ESR1) gene mutations that lead to endocrine resistance and treatment of endocrine resistant ER+ cancers.
    Type: Application
    Filed: October 16, 2020
    Publication date: November 25, 2021
    Inventors: Kaitlyn Andreano, Ching-yi Chang, Donald P. McDonnell, Stephanie L. Gaillard
  • Patent number: 11158533
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first trench, and a second trench. The substrate has a first region and a second region. The first trench is formed in the substrate within the first region. The first trench is surrounded by a first protrusion structure having a top portion and sidewalls. The second trench is formed in the substrate within the second region. The second trench is surrounded by a second protrusion structure having a top portion and sidewalls. The second trench is deeper than the first trench. The connection portion between the top portion and the sidewalls of the second protrusion structure has a greater radius of curvature than the connection portion between the top portion and the sidewalls of the first protrusion structure.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 26, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ching-Yi Hsu, Pi-Kuang Chuang, Po-Sheng Hu
  • Publication number: 20210301881
    Abstract: The present invention relates to a central connector for a universal joint and a universal joint utilizing said central connector. The central connector includes a substantially cylindrical body. The connector further includes a first and second pair of arms positioned orthogonal to one another. The body of the central connector also includes a male spherically concave surface between the first pair of arms, a female spherically concave surface between the second pair of arms. The body further defines an opening allowing communication between the male and female spherically concave surfaces.
    Type: Application
    Filed: March 23, 2021
    Publication date: September 30, 2021
    Inventors: Ching-Yi TU, Yi Tung CHAN
  • Publication number: 20210249536
    Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chin-Hsiu HUANG, Tse-Hsiao LIU, Pao-Hao CHIU, Chih-Cherng LIAO, Ching-Yi HSU
  • Patent number: 11065506
    Abstract: A muscle training system configured to train at least one target muscle of a human body includes a muscle training equipment and a controller. The muscle training equipment includes at least one resistance adjustment assembly and at least one vibration detector. The at least one resistance adjustment assembly is configured to provide a resistance force as a training load. The at least one vibration detector is configured to be disposed on the at least one target muscle and produces at least one muscle vibration signal based on an activity of the at least one target muscle training under the resistance force. The controller is configured to control the at least one resistance adjustment assembly to adjust the resistance force according to the at least one muscle vibration signal.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 20, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsung-Chi Lin, Jyun-Liang Pan, Kai-Jen Pai, Zhong-We Liao, Yen-Chung Chang, Szu-Han Tzao, Ching Yi Liu
  • Patent number: 11051421
    Abstract: A cooling assembly includes a primary plate, a secondary plate, and a padding layer. The primary plate includes a body, a first arm, and a second arm. The first arm and the second arm of the primary plate extend outwardly in opposite directions from the body of the primary plate. The secondary plate also includes a body, a first arm, and a second arm. The first arm and the second arm of the secondary plate extend outwardly in opposite directions from the body of the secondary plate. The padding layer is inserted between the primary plate and the secondary plate. The padding layer directly contacts a heat-generating electrical component secured between the primary plate and the secondary plate.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 29, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yi-Chieh Chen, Yueh-Chang Wu, Ching-Yi Shih
  • Patent number: D930175
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: September 7, 2021
    Assignee: Global Trading and Promotion, Inc.
    Inventors: Albert Arazi, Ching-Yi Tang