Abstract: Embodiments provide a device structure and method of forming a device structure including an infill structure to capture solder materials within confines of openings of the infill structure. Metal pillars of one device can penetrate through a non-conductive film and contact solder regions of another device. A separate underfill is not needed.

Abstract: A light-emitting module is provided. The light-emitting module includes a substrate and n number of light-emitting elements disposed on the substrate. The n number of light-emitting elements have n?1 number of first intervals. The n?1 number of first intervals have a first standard deviation, wherein n is greater than or equal to 3. The light-emitting module further includes a light-shielding structure which is disposed on the n number of light-emitting elements and has n number of light-emitting holes. The n number of light-emitting holes correspond to the n number of light-emitting elements, respectively, and have n?1 number of second intervals. The n?1 number of second intervals have a second standard deviation, wherein the first standard deviation is greater than the second standard deviation.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

Abstract: A method of predicting the efficacy of natural killer cells, including: generating a plurality of training data corresponding to a plurality of donors based on a characteristic factor and a corresponding killing result against the target cancer cells of a plurality of cultured natural killer cells from the donors; obtaining a trained neural network model by inputting the plurality of training data into a neural network model; inputting a to-be-tested input vector corresponding to at least one characteristic factor of a to-be-tested natural killer cell into the trained neural network model to obtain an outputted result vector of the trained neural network model, wherein the result vector indicates a predicted killing result corresponding to the target cancer cell after applying the to-be-tested natural killer cell; and determining a quality of the to-be-tested natural killer cell based on the predicted killing result.

Abstract: An electronic apparatus including a package substrate and a structure disposed on and electrically connected to the package substrate through conductive bumps is provided. The material of the conductive bumps includes a bismuth (Bi) containing alloy or an indium (In) containing alloy. In some embodiments, the bismuth (Bi) containing alloy includes Sn—Ag—Cu—Bi alloy. In some embodiments, a concentration of bismuth (Bi) contained in the Sn—Ag—Cu—Bi alloy ranges from about 1 wt % to about 10 wt %. Methods for forming the Sn—Ag—Cu—Bi alloy are also provided.

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.

Abstract: In an embodiment, a method includes performing a first atomic layer deposition (ALD) process to form a first material layer over a first blank wafer, the first ALD process comprising: performing a first precursor sub-cycle using a first precursor; performing a first purge sub-cycle using a inert gas; and performing a second precursor sub-cycle using a second precursor and the inert gas; and performing a second purge sub-cycle for a first duration over a second blank wafer different from the first blank wafer using the inert gas to deposit first defects onto the second blank wafer.

Abstract: A semiconductor device includes a first gate stack structure over a substrate, a source/drain epitaxial layer, a lightly doped region, and a silicide region. The source/drain epitaxial layer is disposed in the substrate and adjacent to the first gate stack structure. The lightly doped region is located in the substrate to be electrically connected to the source/drain epitaxial layer. The lightly doped region includes a first portion protrudes from a sidewall of the source/drain epitaxial layer. The silicide region is in contact with a top surface and sidewalls of a top portion of the source/drain epitaxial layer and a top surface of the first portion of the lightly doped region. The top portion of the source/drain epitaxial layer is higher than the top surface of the first portion of the lightly doped region.

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

Abstract: An embodiment is a device including a substrate comprising conductive pads, a package component bonded to the conductive pads of the substrate with solder connectors, the package component comprising an integrated circuit die, the integrated circuit die comprising die connectors, one of the solder connectors coupled to each of the die connectors and a corresponding conductive pad of the substrate, a first dielectric layer laterally surrounding each of the die connectors and a portion of the solder connectors, and a second dielectric layer being between the first dielectric layer and the substrate, the second dielectric layer laterally surrounding each of the conductive pads of the substrate.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a frontside and a backside. The workpiece includes a substrate, a first plurality of channel members over a first portion of the substrate, a second plurality of channel members over a second portion of the substrate, an isolation feature sandwiched between the first and second portions of the substrate. The method also includes forming a joint gate structure to wrap around each of the first and second pluralities of channel members, forming a pilot opening in the isolation feature, extending the pilot opening through the join gate structure to form a gate cut opening that separates the joint gate structure into a first gate structure and a second gate structure, and depositing a dielectric material into the gate cut opening to form a gate cut feature.

Abstract: A method of performing a chemical mechanical planarization (CMP) process includes holding a wafer by a retainer ring attached to a carrier, pressing the wafer against a first surface of a polishing pad, the polishing pad rotating at a first speed, dispensing a slurry on the first surface of the polishing pad, and generating vibrations at the polishing pad.

Abstract: A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

Abstract: A fast charging lithium-ion battery includes a positive electrode plate, a negative electrode plate, a separator, and an electrolyte. The positive electrode plate includes a positive current collector and a positive active material layers. The negative electrode plate includes a negative current collector and negative active material layers. The negative active material layers include titanium niobium oxide, lithium titanate, or a combination thereof. The separator is disposed between the positive electrode plate and the negative electrode plate. The electrolyte contacts the positive electrode plate and the negative electrode plate. The negative active material layers have an effective area corresponding to the positive electrode plate. The negative active material layers have a thickness on one surface of the negative current collector. A ratio of the effective area to the thickness is greater than 2×105 mm.

Abstract: A manufacturing process is described to evaluate and select raw semiconductor wafers in preparation for epitaxial layer formation. The manufacturing process first produces a single crystal ingot during which a seed pulling velocity and temperature gradient are closely controlled. The resulting ingot is vacancy-rich with relatively few self-interstitial defects. Selected wafers can advance to a high-temperature nitridation annealing operation that further reduces the number of interstitials while increasing the vacancies. Substrates characterized by a high vacancy density can then be used to optimize an epitaxial layer deposition process.

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).

Abstract: A semiconductor structure includes a barrier layer over a channel layer, and a doped layer over the barrier layer. A gate electrode is over the doped layer and a doped interface layer is formed between the barrier layer and the doped layer. The doped interface layer includes a dopant and a metal. The metal has a metal concentration that follows a gradient function from a highest metal concentration to a lowest metal concentration.

Abstract: A network connection control system and method is provided. The network connection control system includes user equipments, base stations, a server and first and second processing units. Each user equipment transmits a network parameter between it and every base station to the server through the base station connected therewith. The first processing unit assigns CIO set values corresponding to the base station. The network connection control system is configured to perform an optimizing procedure. In the optimizing procedure, according to the CIO set values, the network parameters, the throughput objective function and connection and network resource constraints of all the user equipments and base stations, the first and second processing units processes based on classical algorithm and quantum annealing algorithm respectively to obtain the optimized connection configuration.

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).