Patents by Inventor Ching-Yu Chen

Ching-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150156829
    Abstract: The present invention discloses a light emitting device array billboard and a control method thereof. The light emitting device array billboard includes a light emitting device array circuit, plural line switch circuits, plural channel switch circuits, plural ghost image compensation switch circuits, and a control circuit. The control circuit operates the line switch circuits and the channel switch circuit to turn ON a selected light emitting device for a duty period in a lighting period, and operates the plural ghost image compensation switch circuits to electrically connect a channel node corresponding to the selected light emitting device to a ghost image compensation voltage after the lighting period. The control circuit further adjusts a channel operation signal according to a gray scale compensation signal, to turn ON the selected light emitting device for a gray scale compensation period in addition to the duty period.
    Type: Application
    Filed: November 12, 2014
    Publication date: June 4, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION, R.O.C
    Inventors: Shui-Mu Lin, Chien-Hua Lin, Ching-Yu Chen, Chin-Hui Wang, Yung-Chun Chuang, Ti-Ti Liu
  • Publication number: 20150055671
    Abstract: The present disclosure involves a light-emitting device. The light-emitting device includes an n-doped gallium nitride (n-GaN) layer located over a substrate. A multiple quantum well (MQW) layer is located over the n-GaN layer. An electron-blocking layer is located over the MQW layer. A p-doped gallium nitride (p-GaN) layer is located over the electron-blocking layer. The light-emitting device includes a hole injection layer. In some embodiments, the hole injection layer includes a p-doped indium gallium nitride (p-InGaN) layer that is located in one of the three following locations: between the MQW layer and the electron-blocking layer; between the electron-blocking layer and the p-GaN layer; and inside the p-GaN layer.
    Type: Application
    Filed: November 5, 2014
    Publication date: February 26, 2015
    Inventors: Zhen-Yu Li, Tzu-Te Yang, Hon-Way Lin, Chung-Pao Lin, Kuan-Chun Chen, Ching-Yu Chen, You-Da Lin, Hao-Chung Kuo
  • Publication number: 20150048475
    Abstract: A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Yeu Tsai, Chia-Hui Lin, Ching-Yu Chen, Chui-Ya Peng
  • Patent number: 8940075
    Abstract: A method for fabricating fine reduced iron powders comprises the following steps: heating fine iron oxide powders having a mean particle size of smaller than 20 ?m to a reduction temperature of over 700° C. to reduce the fine iron oxide powder into iron powders that are partially sintered into iron powder agglomerates; and performing a crushing-spheroidizing process on the iron powder agglomerates to obtain individual iron powders having a mean particle size of smaller than 20 ?m. The method can reduce iron oxide powers into iron powders having a rounded shape and a high packing density and a high tap density, which are suitable for the metal injection molding process and the inductor fabrication process. The reduced iron powder may further be processed using an annealing process and a second crushing-spheroidizing process in sequence to further increase the sphericity, packing density, and tap density of the reduced iron powder.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: January 27, 2015
    Assignee: Taiwan Powder Technologies Co., Ltd.
    Inventors: Kuen-Shyang Hwang, Ching-Yu Chen, Yung-Chung Lu
  • Publication number: 20140290918
    Abstract: A heat dissipation module includes a centrifugal fan, a second heat dissipation fin array, and a heat pipe. The centrifugal fan includes an outer housing, a first heat dissipation fin array, an impeller and a rotation-driving device. The outer housing has an axial air inlet and a radial air outlet. The rotation-driving device is located within the outer housing and used to drive the impeller to rotate. The second heat dissipation fin array is attached to the radial air outlet. An end of the heat pipe is in contact with both the second heat dissipation fin array and a flat wall of the outer housing on which the axial air inlet is located.
    Type: Application
    Filed: June 10, 2013
    Publication date: October 2, 2014
    Inventor: Ching-Yu CHEN
  • Publication number: 20140197809
    Abstract: The present invention discloses a switching regulator. The switching regulator converts an input voltage to an output voltage. The switching regulator includes: a power stage circuit, which switches at least one power switch thereof according to a driving signal to convert the input voltage to the output voltage; and a control circuit, which is coupled to the power stage circuit, for generating the driving signal according to a feedback signal. The power stage circuit includes: an active circuit, which includes the power switch and at least one inductor, and is controlled by a driving signal to convert the input voltage to a middle voltage; and a passive circuit, which is coupled to the active circuit, and includes a charge pump for converting the middle voltage to the output voltage.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 17, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ching-Yu Chen, Feng-Wei Lin, Kwang-Jae Kim
  • Publication number: 20140132165
    Abstract: The present invention discloses a light emitting device array billboard and a row switch circuit and a control method thereof. The light emitting device array billboard includes a light emitting device array circuit, plural row switch circuits, plural column driver circuits, and a control circuit. The light emitting device array circuit includes plural light emitting devices arranged by columns and rows. Each row switch circuit determines whether to electrically connect a row conduction voltage to the corresponding row node or to discharge charges at the corresponding row node through a discharging path according to a row selection signal. Each column driver circuit determines whether or not to electrically connect a column conduction voltage to the corresponding column node according to a column selection signal. The control circuit provides the row selection signal and the column selection signal to the row switch circuits and the column driver circuits.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 15, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION, R.O.C
    Inventors: Shui-Mu Lin, Ching-Yu Chen, Chien-Hua Lin, Ti-Ti Liu, Kuan-Cheng Lai
  • Publication number: 20140077153
    Abstract: The present disclosure involves a light-emitting device. The light-emitting device includes an n-doped gallium nitride (n-GaN) layer located over a substrate. A multiple quantum well (MQW) layer is located over the n-GaN layer. An electron-blocking layer is located over the MQW layer. A p-doped gallium nitride (p-GaN) layer is located over the electron-blocking layer. The light-emitting device includes a hole injection layer. In some embodiments, the hole injection layer includes a p-doped indium gallium nitride (p-InGaN) layer that is located in one of the three following locations: between the MQW layer and the electron-blocking layer; between the electron-blocking layer and the p-GaN layer; and inside the p-GaN layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: TSMC Solid State Lighting Ltd.
    Inventors: Zhen-Yu Li, Tzu-Te Yang, Hon-Way Lin, Chung-Pao Lin, Kuan-Chun Chen, Ching-Yu Chen, You-Da Lin, Hao-Chung Kuo
  • Publication number: 20140055995
    Abstract: An illumination apparatus includes a frame, an optical base plate, a light source and an optical film. The optical base plate is disposed in the frame and has a first protrusion portion at the center of the optical base plate. The first protrusion portion has at least a reflective surface and a top surface, which are connected with each other. The light source is disposed in the frame and located adjacent to the periphery of the optical base plate. The light source is disposed corresponding to the reflective surface and has a plurality of light-emitting elements. Each light-emitting element has an optical axis direction, and the optical axis directions extend toward the first protrusion portion. The optical film is disposed at the frame, and the first protrusion portion of the optical base plate protrudes toward the optical film.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 27, 2014
    Applicant: SOUTHERN TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: CHIH-CHIEH KANG, JENG-FENG LIN, CHING-YU CHEN, SYUE-AN CENG, KAI-MING CHUANG, YU-RUI YANG
  • Publication number: 20140055994
    Abstract: An illumination apparatus includes a frame, an optical base plate, a light source and an optical film. The optical base plate is disposed in the frame and has a protrusion area at the center of the optical base plate. The protrusion area has at least a protrusion portion, which has at least a reflective surface. The reflective surface includes a plurality of inclined surfaces with different inclination angles. The light source is disposed in the frame and located adjacent to the periphery of the optical base plate. The light source is disposed corresponding to the reflective surface and has a plurality of light-emitting elements. Each light-emitting element has an optical axis direction, and the optical axis directions extend toward the protrusion area. The optical film is disposed at the frame, and the protrusion portion of the optical base plate protrudes toward the optical film.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 27, 2014
    Applicant: Southern Taiwan University of Science and Technology
    Inventors: CHIH-CHIEH KANG, JENG-FENG LIN, CHING-YU CHEN, SYUE-AN CENG, KAI-MING CHUANG, YU-RUI YANG
  • Publication number: 20130263698
    Abstract: A method for fabricating fine reduced iron powders comprises the following steps: heating fine iron oxide powders having a mean particle size of smaller than 20 ?m to a reduction temperature of over 700° C. to reduce the fine iron oxide powder into iron powders that are partially sintered into iron powder agglomerates; and performing a crushing-spheroidizing process on the iron powder agglomerates to obtain individual iron powders having a mean particle size of smaller than 20 ?m. The method can reduce iron oxide powers into iron powders having a rounded shape and a high packing density and a high tap density, which are suitable for the metal injection molding process and the inductor fabrication process. The reduced iron powder may further be processed using an annealing process and a second crushing-spheroidizing process in sequence to further increase the sphericity, packing density, and tap density of the reduced iron powder.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Inventors: Kuen-Shyang HWANG, Ching-Yu Chen, Yung-Chung Lu
  • Patent number: 8225179
    Abstract: A method for generating error detection code is disclosed. Firstly, a first error detection code PEDC is derived by using 12-byte unknown sector data information including ID, IED, RSV and the 2048-byte main data while the main data is delivered from a host. Secondly, a second error detection code MEDC is obtained by using known 12-byte sector data information including ID, IED, RSV and the 2048-byte main data. Thereafter, the real error detection code EDC is obtained by applying an exclusive-OR operation to both the PEDC and MEDC.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 17, 2012
    Assignee: Tian Holdings, LLC
    Inventors: Chiung-Ying Peng, Ching-Yu Chen
  • Publication number: 20110155061
    Abstract: A reactor for film deposition having a first heating unit and the second heating units is described. The temperature of each heating unit is controlled individually by heating and/or cooling means. The first heating unit and the second heating unit are disposed face-to-face to each other to form a reaction region therein, and their inner sides are placed with an inclined angle. At least one substrate is disposed on the inner surface of the first heating unit. The temperature of the second heating unit can be adapted to a temperature higher than the temperature of the first heating unit to improve the thermal decomposition efficiency of input reactants so that a low-temperature film deposition can be accomplished.
    Type: Application
    Filed: November 15, 2010
    Publication date: June 30, 2011
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Wei-Kuo CHEN, Ching-Yu CHEN
  • Publication number: 20100151228
    Abstract: The invention provides a reworkable liquid crystal film, including a first substrate, a first conductive layer disposed on the first substrate, and a liquid crystal layer disposed on the first conductive layer. The liquid crystal layer contains microencapsulated liquid crystal droplets dispersed in a thermoplastic polymer matrix. The invention also provides a method for forming the reworkable liquid crystal film.
    Type: Application
    Filed: April 3, 2009
    Publication date: June 17, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Lung CHIN, Chang-Hung WU, Shih-Hsien LIU, Kung-Lung CHENG, Yih-Her CHANG, Jer-Young CHEN, Ching-Yu CHEN
  • Patent number: 7716556
    Abstract: A method applied to an optical disc drive for calculating an error detection code corresponding to a data sector is disclosed. The data sector includes a plurality of bytes arranged in a matrix having N lines along a first direction and M lines along a second direction perpendicular to the first direction. The method includes: along the first direction, calculating error detection codes corresponding to M bytes located at each of the N lines, wherein for each of the N lines, only bytes having error bits affect an error detection code for the line; adjusting an error detection code of each of the N lines according to a displacement between each of the N lines and a last line of the N lines; and then determining the error detection code of the data sector by summing up the displacement-adjusted error detection code of each of the N lines.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: May 11, 2010
    Assignee: VIA Optical Solution, Inc.
    Inventor: Ching-Yu Chen
  • Patent number: 7560338
    Abstract: A nonvolatile memory consisting of a substrate, a dielectric layer, word lines, word gates, conductive spacers, electron trapping layer, insulation layer and buried bit lines is provided. The dielectric layer is on the substrate and has several poly trenches thereon, and the word lines are disposed over the substrate across the poly trenches. The word gates are in the poly trenches between the word lines and the substrate, and the conductive spacers are between the word gates and the inner wall of each poly trench. The electron trapping layer is disposed between the conductive spacers and the inner wall of each poly trench and between the conductive spacers and the substrate. The insulation layer is between the conductive spacers and the word gates. The buried bit lines are in the substrate between the poly trenches.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: July 14, 2009
    Assignee: Winbond Electronics Corp.
    Inventors: Hsiu-Han Liao, Chi-Hung Chao, Ching-Yu Chen
  • Publication number: 20090077452
    Abstract: A method for generating error detection code is disclosed. Firstly, a first error detection code PEDC is derived by using 12-byte unknown sector data information including ID, IED, RSV and the 2048-byte main data while the main data is delivered from a host. Secondly, a second error detection code MEDC is obtained by using known 12-byte sector data information including ID, IED, RSV and the 2048-byte main data. Thereafter, the real error detection code EDC is obtained by applying an exclusive-OR operation to both the PEDC and MEDC.
    Type: Application
    Filed: September 12, 2008
    Publication date: March 19, 2009
    Inventors: Chiung-Ying Peng, Ching-Yu Chen
  • Patent number: 7426682
    Abstract: A method for generating error detection code is disclosed. Firstly, a first error detection code PEDC is derived by using 12-byte unknown sector data information including ID, IED, RSV and the 2048-byte main data while the main data is delivered from a host. Secondly, a second error detection code MEDC is obtained by using known 12-byte sector data information including ID, IED, RSV and the 2048-byte main data. Thereafter, the real error detection code EDC is obtained by applying an exclusive-OR operation to both the PEDC and MEDC.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: September 16, 2008
    Assignee: Via Technologies, Inc.
    Inventors: Chiung-Ying Peng, Ching-Yu Chen
  • Patent number: 7293220
    Abstract: An apparatus and method for accessing data from a storage medium is disclosed. The apparatus fetches a data block from the storage medium via an accessing unit, and corrects an error of the data block by an error correction code (ECC) decoder according to an ECC of the data block. The apparatus also includes an error detection code (EDC) processor for calculating an EDC of each data sector of the data block, and a flag register for storing a flag associated with each data sector. The method includes re-fetching a data sector if the associated flag indicates the EDC of the data sector is incorrect; and bypassing a data sector if the associated flag indicates that the EDC of the data sector is correct, even though the ECC of the data block indicates that the data sector contains an error.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: November 6, 2007
    Assignee: Via Technologies, Inc.
    Inventors: Dao-Ning Guo, Ching-Yu Chen, Meng-Huang Chu, Pei-Jei Hu
  • Publication number: 20070207556
    Abstract: A nonvolatile memory consisting of a substrate, a dielectric layer, word lines, word gates, conductive spacers, electron trapping layer, insulation layer and buried bit lines is provided. The dielectric layer is on the substrate and has several poly trenches thereon, and the word lines are disposed over the substrate across the poly trenches. The word gates are in the poly trenches between the word lines and the substrate, and the conductive spacers are between the word gates and the inner wall of each poly trench. The electron trapping layer is disposed between the conductive spacers and the inner wall of each poly trench and between the conductive spacers and the substrate. The insulation layer is between the conductive spacers and the word gates. The buried bit lines are in the substrate between the poly trenches.
    Type: Application
    Filed: May 11, 2007
    Publication date: September 6, 2007
    Applicant: WINBOND ELECTRONICS CORP.
    Inventors: Hsiu-Han Liao, Chi-Hung Chao, Ching-Yu Chen