Patents by Inventor Ching-Yu Hung

Ching-Yu Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10700177
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Hsiu Hung, Yi-Hsiang Chao, Kuan-Yu Yeh, Kan-Ju Lin, Chun-Wen Nieh, Huang-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Publication number: 20200106156
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Application
    Filed: April 18, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Patent number: 10375712
    Abstract: A time-division mechanism that a source station uses a proprietary frame for notifying switching from a normal bandwidth operation to a narrow bandwidth operation to at least one destination station in a wireless communication system, and uses a protection frame to reserve the service period for the narrow bandwidth operation without the interference from the normal bandwidth operation, wherein the service period of the narrow bandwidth operation is indicated in the protection frame.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 6, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tsai-Yuan Hsu, Chieh-Chao Liu, Shih-Chung Yin, Kun-Chien Hung, Ching-Yu Kuo, Hung-Pin Ma
  • Patent number: 9519617
    Abstract: A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: December 13, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ching-Yu Hung, Shinri Inamori, Jagadeesh Sankaran, Peter Chang
  • Patent number: 9092228
    Abstract: A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: July 28, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alan L. Davis, Ching-Yu Hung, Jadadeesh Sankaran, James Nagurne, Mel Alan Phipps, Ajay Jayaraj
  • Patent number: 8619866
    Abstract: A method for processing digital image data is provided that includes compressing a block of the digital image data to generate a compressed block, storing the compressed block in an external memory when a number of bits in the compressed block does not exceed a first compression threshold, and storing the block in the external memory when the number of bits in the compressed block exceeds the first compression threshold.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: December 31, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Minhua Zhou, Ching-Yu Hung
  • Publication number: 20130185540
    Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core includes a program memory interface through which the scalar processor retrieves instructions from a program memory. The instructions include scalar instructions executable by the scalar processor and vector instructions executable by the vector coprocessor core. The vector coprocessor core includes a plurality of execution units and a vector command buffer. The vector command buffer is configured to decode vector instructions passed by the scalar processor core, to determine whether vector instructions defining an instruction loop have been decoded, and to initiate execution of the instruction loop by one or more of the execution units based on a determination that all of the vector instructions of the instruction loop have been decoded.
    Type: Application
    Filed: July 13, 2012
    Publication date: July 18, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ching-Yu HUNG, Shinri INAMORI, Jagadeesh SANKARAN, Peter CHANG
  • Publication number: 20130185539
    Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.
    Type: Application
    Filed: July 13, 2012
    Publication date: July 18, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ching-Yu HUNG, Shinri INAMORI, Jagadeesh SANKARAN, Peter CHANG
  • Publication number: 20130185538
    Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage. The instruction stream includes scalar instructions executable by the scalar processor core and vector instructions executable by the vector coprocessor core. The scalar processor core is configured to pass the vector instructions to the vector coprocessor core. The vector coprocessor core configured to process a plurality of data values in parallel while executing each vector instruction passed by the scalar processor core. The vector coprocessor core includes a plurality of processing paths arranged in parallel to process the data values. Each of the processing paths includes an execution unit. Each of the execution units is configured to communicate a result of processing to each other of the execution units.
    Type: Application
    Filed: July 13, 2012
    Publication date: July 18, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ching-Yu Hung, Shinri Inamori, Jagadeesh Sankaran, Peter Chang
  • Publication number: 20130185544
    Abstract: A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.
    Type: Application
    Filed: July 13, 2012
    Publication date: July 18, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ching-Yu HUNG, Shinri INAMORI, Jagadeesh SANKARAN, Peter CHANG
  • Patent number: 8111760
    Abstract: Deblock filtering for Microsoft WMV video decoders partitions the computation so that the deblock filtering operations can be performed on horizontal or vertical stripes or in one pass on oversized macroblocks.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Ching-Yu Hung, Ngai-Man Cheung
  • Publication number: 20110080956
    Abstract: A method for processing digital image data is provided that includes compressing a block of the digital image data to generate a compressed block, storing the compressed block in an external memory when a number of bits in the compressed block does not exceed a first compression threshold, and storing the block in the external memory when the number of bits in the compressed block exceeds the first compression threshold.
    Type: Application
    Filed: October 2, 2009
    Publication date: April 7, 2011
    Inventors: Minhua Zhou, Ching-Yu Hung
  • Patent number: 7797362
    Abstract: An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: September 14, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Nara Won, Ching-Yu Hung
  • Publication number: 20100168261
    Abstract: Foam is provided. The foam includes starch, wood flour, a chemical auxiliary and resin, wherein the resin has a weight ratio exceeding 50%. The invention also provides a method for fabricating the foam. The method includes providing a foam raw material including starch, wood flour, a chemical auxiliary and resin, wherein the resin has a weight ratio exceeding 50%, blending the foam raw material and a foaming fluid to form a blend, and performing a foaming process to form foam.
    Type: Application
    Filed: February 18, 2009
    Publication date: July 1, 2010
    Applicant: WISTRON CORP
    Inventors: Ching-Yu Hung, Li-Sheng Teng
  • Patent number: 7728840
    Abstract: A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial input data array and performing an image data array operation on the input data array. The method repeats the following steps for plural iterations including loading the data buffer with new input data forming a new input data array for a next iteration and performing the input data array operation on the new input data array. The overlap data consists of pixels at an end of each scan line. Loading new input data includes loading pixels following the overlap data for each scan line.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: June 1, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Ching-Yu Hung
  • Publication number: 20100110222
    Abstract: A video processing front-end for digital cameras, camcorders, video cell phones, et cetera has multiple interconnected processing modules for functions such as CCD controller, preview engine, auto exposure, auto focus, auto white balance, et cetera with complicated data flow can be realized and managed.
    Type: Application
    Filed: January 18, 2010
    Publication date: May 6, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: David E. Smith, Deependra Talla, Clay Dunsmore, Ching-Yu Hung
  • Patent number: 7593580
    Abstract: A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (30A) captures and encodes a first group of frames, and instructs a slave image processor (30B) to capture and encode a second group of frames presented by the CCD imager (22) before the encoding of the first group of frames is completed by the master image processor. The master image processor (30A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (30B) are transferred to the master image processor (30A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (36A; 38).
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: September 22, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Damon Domke, Youngjun Yoo, Deependra Talla, Ching-Yu Hung
  • Patent number: 7502075
    Abstract: A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The central memory interface accepts read and write memory the said plurality of processing modules and issues burst memory access requests to an external memory by gathering plural memory access requests from the processing modules.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: March 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: David E. Smith, Deependra Talla, Ching-Yu Hung
  • Publication number: 20080208942
    Abstract: An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 28, 2008
    Inventors: Nara Won, Ching-Yu Hung
  • Patent number: D851038
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: June 11, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wan-Chen Peng, Ruei-Lin Hung, Ching-Yu Cheng