Patents by Inventor Ching-Yu Hung
Ching-Yu Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9092228Abstract: A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language.Type: GrantFiled: January 17, 2013Date of Patent: July 28, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Alan L. Davis, Ching-Yu Hung, Jadadeesh Sankaran, James Nagurne, Mel Alan Phipps, Ajay Jayaraj
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Patent number: 8619866Abstract: A method for processing digital image data is provided that includes compressing a block of the digital image data to generate a compressed block, storing the compressed block in an external memory when a number of bits in the compressed block does not exceed a first compression threshold, and storing the block in the external memory when the number of bits in the compressed block exceeds the first compression threshold.Type: GrantFiled: October 2, 2009Date of Patent: December 31, 2013Assignee: Texas Instruments IncorporatedInventors: Minhua Zhou, Ching-Yu Hung
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Publication number: 20130185538Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage. The instruction stream includes scalar instructions executable by the scalar processor core and vector instructions executable by the vector coprocessor core. The scalar processor core is configured to pass the vector instructions to the vector coprocessor core. The vector coprocessor core configured to process a plurality of data values in parallel while executing each vector instruction passed by the scalar processor core. The vector coprocessor core includes a plurality of processing paths arranged in parallel to process the data values. Each of the processing paths includes an execution unit. Each of the execution units is configured to communicate a result of processing to each other of the execution units.Type: ApplicationFiled: July 13, 2012Publication date: July 18, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ching-Yu Hung, Shinri Inamori, Jagadeesh Sankaran, Peter Chang
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Publication number: 20130185544Abstract: A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.Type: ApplicationFiled: July 13, 2012Publication date: July 18, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ching-Yu HUNG, Shinri INAMORI, Jagadeesh SANKARAN, Peter CHANG
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Publication number: 20130185540Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core includes a program memory interface through which the scalar processor retrieves instructions from a program memory. The instructions include scalar instructions executable by the scalar processor and vector instructions executable by the vector coprocessor core. The vector coprocessor core includes a plurality of execution units and a vector command buffer. The vector command buffer is configured to decode vector instructions passed by the scalar processor core, to determine whether vector instructions defining an instruction loop have been decoded, and to initiate execution of the instruction loop by one or more of the execution units based on a determination that all of the vector instructions of the instruction loop have been decoded.Type: ApplicationFiled: July 13, 2012Publication date: July 18, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ching-Yu HUNG, Shinri INAMORI, Jagadeesh SANKARAN, Peter CHANG
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Publication number: 20130185539Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.Type: ApplicationFiled: July 13, 2012Publication date: July 18, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ching-Yu HUNG, Shinri INAMORI, Jagadeesh SANKARAN, Peter CHANG
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Patent number: 8111760Abstract: Deblock filtering for Microsoft WMV video decoders partitions the computation so that the deblock filtering operations can be performed on horizontal or vertical stripes or in one pass on oversized macroblocks.Type: GrantFiled: November 16, 2006Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Ching-Yu Hung, Ngai-Man Cheung
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Publication number: 20110080956Abstract: A method for processing digital image data is provided that includes compressing a block of the digital image data to generate a compressed block, storing the compressed block in an external memory when a number of bits in the compressed block does not exceed a first compression threshold, and storing the block in the external memory when the number of bits in the compressed block exceeds the first compression threshold.Type: ApplicationFiled: October 2, 2009Publication date: April 7, 2011Inventors: Minhua Zhou, Ching-Yu Hung
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Patent number: 7797362Abstract: An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.Type: GrantFiled: February 23, 2007Date of Patent: September 14, 2010Assignee: Texas Instruments IncorporatedInventors: Nara Won, Ching-Yu Hung
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Publication number: 20100168261Abstract: Foam is provided. The foam includes starch, wood flour, a chemical auxiliary and resin, wherein the resin has a weight ratio exceeding 50%. The invention also provides a method for fabricating the foam. The method includes providing a foam raw material including starch, wood flour, a chemical auxiliary and resin, wherein the resin has a weight ratio exceeding 50%, blending the foam raw material and a foaming fluid to form a blend, and performing a foaming process to form foam.Type: ApplicationFiled: February 18, 2009Publication date: July 1, 2010Applicant: WISTRON CORPInventors: Ching-Yu Hung, Li-Sheng Teng
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Patent number: 7728840Abstract: A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial input data array and performing an image data array operation on the input data array. The method repeats the following steps for plural iterations including loading the data buffer with new input data forming a new input data array for a next iteration and performing the input data array operation on the new input data array. The overlap data consists of pixels at an end of each scan line. Loading new input data includes loading pixels following the overlap data for each scan line.Type: GrantFiled: September 7, 2004Date of Patent: June 1, 2010Assignee: Texas Instruments IncorporatedInventor: Ching-Yu Hung
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Publication number: 20100110222Abstract: A video processing front-end for digital cameras, camcorders, video cell phones, et cetera has multiple interconnected processing modules for functions such as CCD controller, preview engine, auto exposure, auto focus, auto white balance, et cetera with complicated data flow can be realized and managed.Type: ApplicationFiled: January 18, 2010Publication date: May 6, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: David E. Smith, Deependra Talla, Clay Dunsmore, Ching-Yu Hung
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Patent number: 7593580Abstract: A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master image processor (30A) captures and encodes a first group of frames, and instructs a slave image processor (30B) to capture and encode a second group of frames presented by the CCD imager (22) before the encoding of the first group of frames is completed by the master image processor. The master image processor (30A) completes its encoding, and is then available to capture and encode another group of frames in the sequence. Video frames that are encoded by the slave image processor (30B) are transferred to the master image processor (30A), which sequences and stores the transferred encoded frames and also those frames that it encodes in a memory (36A; 38).Type: GrantFiled: July 13, 2004Date of Patent: September 22, 2009Assignee: Texas Instruments IncorporatedInventors: Damon Domke, Youngjun Yoo, Deependra Talla, Ching-Yu Hung
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Patent number: 7502075Abstract: A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The central memory interface accepts read and write memory the said plurality of processing modules and issues burst memory access requests to an external memory by gathering plural memory access requests from the processing modules.Type: GrantFiled: September 6, 2005Date of Patent: March 10, 2009Assignee: Texas Instruments IncorporatedInventors: David E. Smith, Deependra Talla, Ching-Yu Hung
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Publication number: 20080208942Abstract: An extension to current multiple memory bank video processing architecture is presented. A more powerful memory controller is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.Type: ApplicationFiled: February 23, 2007Publication date: August 28, 2008Inventors: Nara Won, Ching-Yu Hung
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Publication number: 20080117980Abstract: Deblock filtering for Microsoft WMV video decoders partitions the computation so that the deblock filtering operations can be performed on horizontal or vertical stripes or in one pass on oversized macroblocks.Type: ApplicationFiled: November 16, 2006Publication date: May 22, 2008Inventors: Ching-Yu Hung, Ngai-Man Cheung
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Patent number: 7362362Abstract: A programmable data reformatter reorders output from an image sensor to yield various formats. The reformatting applies to reduced resolution output from large image sensors as in digital cameras operating in video mode, and converts an irregular video mode output to a standard format, such as Bayer pattern, for image processing.Type: GrantFiled: July 9, 2004Date of Patent: April 22, 2008Assignee: Texas Instruments IncorporatedInventors: Deependra Talla, Clay Dunsmore, Ching-Yu Hung
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Patent number: 7333141Abstract: Polyphase filtering, such as resampling for image resizing, on a processor with parallel output units is cast in terms of data access blocks and data coverage charts to increase processor efficiency. Automatic generation of implementations corresponding to input resampling factors by computation cost comparisons.Type: GrantFiled: October 22, 2003Date of Patent: February 19, 2008Assignee: Texas Instruments IncorporatedInventor: Ching-Yu Hung
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Patent number: 7176815Abstract: Context-based adapative binary arithmetic coding (CABAC), as used in video standards such as H.264/AVC, with a renormalization of the interval low value plus range that includes partitioning of the bits of the low value to provide output bits plus low value update without bit-level iterations or aggregation of output bits until a full byte can be output.Type: GrantFiled: September 26, 2005Date of Patent: February 13, 2007Assignee: Texas Instruments IncorporatedInventors: Ching-Yu Hung, Shraddha Gondkar, Jagadeesh Sankaran
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Publication number: 20060007332Abstract: A programmable data reformatter reorders output from an image sensor to yield various formats. The reformatting applies to reduced resolution output from large image sensors as in digital cameras operating in video mode, and converts an irregular video mode output to a standard format, such as Bayer pattern, for image processing.Type: ApplicationFiled: July 9, 2004Publication date: January 12, 2006Inventors: Deependra Talla, Clay Dunsmore, Ching-Yu Hung