Abstract: A biochip packaging structure includes a chip packaging layer, a redistribution layer, and a microfluidic channel. The chip packaging layer includes a resin layer including a biochip and a conductive pillar located on each of two sides of the biochip. The biochip includes a first surface flush with and exposed out of a side of the resin layer. A first end of the conductive pillar is flush with a side of the resin layer opposite the biochip. A second end of the conductive pillar is flush with the first surface of the biochip. The redistribution layer includes a metal winding electrically coupled to the biochip and the adjacent conductive pillar. The metal winding includes a first winding portion coupled to the biochip and a second winding portion coupled between the first winding portion and the conductive pillar. The second winding portion is parallel to the first surface.

Abstract: A package structure includes a first chip, a first redistribution layer, a second chip, a second redistribution layer, a third redistribution layer, a carrier, and a first molding compound layer. The first redistribution layer is arranged on a surface of the first chip. The second redistribution layer is arranged on a surface of the second chip. The third redistribution layer interconnects the first redistribution layer and the second redistribution layer. The carrier is arranged on a side of the third redistribution layer away from the first redistribution layer and the second redistribution layer. The first molding compound layer covers the first chip, the first redistribution layer, the second chip, and the second redistribution layer. A manufacturing method is also disclosed.

Abstract: A semiconductor packaging structure manufactured in a manner which does not leave the chip damaged or susceptible to damage upon the removal of temporary manufacturing supports includes at least one electrical conductor, at least one conductive layer, a chip, and a colloid. The chip is spaced from the conductive layer, the electrical conductor is disposed between the conductive layer and the chip and electrically connects the conductive layer to the chip. The colloid covers all outer surfaces of the chip. A method of fabricating such a semiconductor packaging structure is also provided.

Abstract: A fan-out packaging structure includes a redistribution layer and a positioning sheet formed on the redistribution layer. The positioning sheet defines at least one opening penetrating opposite sides of the positioning sheet. At least one chip is mounted in the at least one opening. The redistribution layer comprises at least one conductive circuit. The at least one chip is electrically coupled to a corresponding one conductive circuit.

Abstract: A fan-out packaging structure includes a redistribution layer and a positioning sheet formed on the redistribution layer. The positioning sheet defines at least one opening penetrating opposite sides of the positioning sheet. At least one chip is mounted in the at least one opening. The redistribution layer comprises at least one conductive circuit. The at least one chip is electrically coupled to a corresponding one conductive circuit.

Abstract: Packaging structure includes a first packaging component and a second packaging component arranged in the first packaging component. The packaging component includes a first substrate, a first redistribution layer, a first electronic component, and a first packaging body. The first redistribution layer is arranged on the first substrate. The first electronic component is arranged on the first redistribution layer and electrically coupled to the first redistribution layer. The first packaging body is arranged on the first substrate and covers the first electronic component. The second packaging component includes a second substrate, a second redistribution layer, a second electronic component, and a second packaging body. The redistribution layer is arranged on the second substrate and electrically coupled to the first redistribution layer. The second electronic component is arranged on the second redistribution layer and electrically coupled to the second redistribution layer.

Abstract: A package structure includes a first chip, a first redistribution layer, a second chip, a second redistribution layer, a third redistribution layer, a carrier, and a first molding compound layer. The first redistribution layer is arranged on a surface of the first chip. The second redistribution layer is arranged on a surface of the second chip. The third redistribution layer interconnects the first redistribution layer and the second redistribution layer. The carrier is arranged on a side of the third redistribution layer away from the first redistribution layer and the second redistribution layer. The first molding compound layer covers the first chip, the first redistribution layer, the second chip, and the second redistribution layer. A manufacturing method is also disclosed.

Abstract: A method for making a biochip structure, includes: providing a substrate and forming a plurality of biochips on a surface of the substrate; forming a carrier on a side of the substrate having the biochips, defining a plurality of through holes in the substrate from a side of the substrate away from the carrier; and filling conductive material in each of the through holes to connect one of the biochips. The carrier defines a plurality of openings. Each opening cooperates with substrate to form a micro-channel, and one of the biochips is exposed in the micro-channel.

Abstract: A fingerprint identification chip package of reduced thickness in not requiring a supporting substrate includes a packaging material layer, a fingerprint identification chip in the packaging material layer, conductive pillars in the packaging material layer for structural support, the pillars being spaced apart from the fingerprint identification chip, and a redistribution layer on a side of the packaging material layer. The redistribution layer includes connecting wires, each wire is electrically coupled between the fingerprint identification chip and one conductive pillar. A plurality of pins is on a side of the packaging material layer opposite to the redistribution layer, each pin is electrically coupled to one conductive pillar.

Abstract: A chip packaging structure with better reliability includes a first protective layer, a redistribution layer formed on the first protective layer, at least one chip electrically connected to the redistribution layer, and an encapsulating layer covering the redistribution layer, the chip, and the side surfaces of the first protective layer. The first protective layer comprises an exposed surface and at least four side surfaces each connected to the exposed surface. A plurality of second openings is defined in the second protective layer, and a portion of the redistribution layer is exposed from the plurality of second openings.

Abstract: A biochip packaging structure includes a chip packaging layer, a redistribution layer, and a microfluidic channel. The chip packaging layer includes a resin layer including a biochip and a conductive pillar located on each of two sides of the biochip. The biochip includes a first surface flush with and exposed out of a side of the resin layer. A first end of the conductive pillar is flush with a side of the resin layer opposite the biochip. A second end of the conductive pillar is flush with the first surface of the biochip. The redistribution layer includes a metal winding electrically coupled to the biochip and the adjacent conductive pillar. The metal winding includes a first winding portion coupled to the biochip and a second winding portion coupled between the first winding portion and the conductive pillar. The second winding portion is parallel to the first surface.

Abstract: A package structure includes a first substrate, a first redistribution layer, a second substrate, a carrier chip, a first package, and a patch antenna. The first substrate is grooved for receiving the first redistribution layer. The first redistribution layer is provided with a reflector. The second substrate located on a side of the first substrate has a second redistribution layer which is electrically connected to the first redistribution layer. The carrier chip is on the second substrate and electrically connected to the second redistribution layer. The first package encases the first redistribution layer, the second redistribution layer, the second substrate, and the carrier chip. The patch antenna is on a side of the first package away from the first substrate. A packaged structure array and a manufacturing method thereof are further disclosed.

Abstract: A fan-out packaging structure includes a redistribution layer and a positioning sheet formed on the redistribution layer. The positioning sheet defines at least one opening penetrating opposite sides of the positioning sheet. At least one chip is mounted in the at least one opening. The redistribution layer comprises at least one conductive circuit. The at least one chip is electrically coupled to a corresponding one conductive circuit.

Abstract: A packaging structure for an image sensor includes a circuit board, an image sensor, a first installation bracket, and a second installation bracket. The image sensor is fixed on the circuit board via a first adhesive layer with high viscosity. The first installation bracket is fixed on the image sensor via a second adhesive layer with less (lower) viscosity. The second installation bracket is sleeved on an outside of the first installation bracket and is fixed on the circuit board via a third adhesive layer with a low (the lowest) viscosity. In assembly, relative positionings of the image sensor, the first installation bracket, and the second installation bracket in that order can be performed and adjusted without disturbing earlier positionings, thus any misalignment of the image sensor can be avoided or reduced, and the quality of the packaging structure is improved.

Abstract: A semiconductor packaging structure manufactured in a manner which does not leave the chip damaged or susceptible to damage upon the removal of temporary manufacturing supports includes at least one electrical conductor, at least one conductive layer, a chip, and a colloid. The chip is spaced from the conductive layer, the electrical conductor is disposed between the conductive layer and the chip and electrically connects the conductive layer to the chip. The colloid covers all outer surfaces of the chip. A method of fabricating such a semiconductor packaging structure is also provided.

Abstract: A chip packaging structure with better reliability includes a first protective layer, a redistribution layer formed on the first protective layer, at least one chip electrically connected to the redistribution layer, and an encapsulating layer covering the redistribution layer, the chip, and the side surfaces of the first protective layer. The first protective layer comprises an exposed surface and at least four side surfaces each connected to the exposed surface. A plurality of second openings is defined in the second protective layer, and a portion of the redistribution layer is exposed from the plurality of second openings.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat