Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

Abstract: A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: An electronic device and fabrication method thereof are provided. The electronic device contains a glass substrate, a patterned semiconductor substrate, having at least one opening, disposed on the glass substrate and at least one passive component having a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed between the patterned semiconductor substrate and the glass substrate.

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.