Abstract: A photoresist layer is coated over a wafer. The photoresist layer includes a metal-containing material. An extreme ultraviolet (EUV) lithography process is performed to the photoresist layer to form a patterned photoresist. The wafer is cleaned with a cleaning fluid to remove the metal-containing material. The cleaning fluid includes a solvent having Hansen solubility parameters of delta D in a range between 13 and 25, delta P in a range between 3 and 25, and delta H in a range between 4 and 30. The solvent contains an acid with an acid dissociation constant less than 4 or a base with an acid dissociation constant greater than 9.

Abstract: A photoresist includes a core group that contains metal, and one or more first ligands or one or more second ligands attached to the core group. The first ligands each have a following structure: The second ligands each have a following structure: represents the core group. L? represents a chemical that includes 0˜2 carbon atoms saturated by Hydrogen (H) or Fluorine (F). L represents a chemical that includes 1˜6 carbon atoms saturated by H or F. L? represents a chemical that includes 1˜6 carbon atoms saturated by H. L?? represents a chemical that includes 1˜6 carbon atoms saturated by H or F. Linker represents a chemical that links L? and L?? together.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

Abstract: Embodiments utilize a photoetching process in forming a patterned target layer. After forming a patterned mandrel layer and spacer layer over the patterned mandrel layer, a bottom layer of a photomask is deposited using a chemical vapor deposition process to form an amorphous carbon film. An upper layer of the photomask is used to pattern the bottom layer to form openings for a reverse material. The reverse material is deposited in the openings of the bottom layer, the bottom layer providing both a mask and template function for the reverse material.

Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber; a substrate stage provided in the processing chamber and being configured to secure and rotate a semiconductor wafer; a gas injector configured to inject a chemical to the processing chamber; a window attached to the gas injector; and an adjustable fastening device coupled with the gas injector and the window.

Abstract: Embodiments herein provide techniques related to a NEF. An example technique includes identifying, from an AF that implements a ML model, a request related to reservation of resources for a plurality of AF sessions, wherein the plurality of AF sessions relate to respective UEs of a plurality of UEs, and wherein the request includes an indication of addresses of respective UEs of the plurality of UEs and a QoS parameter; transmitting, to a BSF of the cellular network, a discovery request related to discovery of respective PCFs that are serving the respective UEs of the plurality of UEs; identifying, based on the discovery request, a discovery response that includes indications of the PCFs; identifying, based on the indications of the PCFs and the QoS parameter, a result related to the reservation of resources; and transmitting, to the AF, an indication of the result. Other embodiments may be described and/or claimed.

Abstract: In a method of manufacturing a reflective mask, an adhesion layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer disposed over the substrate, a capping layer disposed over the reflective multilayer, an absorber layer disposed over the capping layer, and a hard mask layer disposed over the absorber layer. A photoresist pattern is formed over the adhesion layer, the adhesion layer is patterned, the hard mask layer is patterned, and the absorber layer is patterned using the patterned hard mask layer as an etching mask. The photoresist layer has a higher adhesiveness to the adhesion layer than to the hard mask layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The method includes exposing a portion of the resist layer. The resist layer includes a photoacid generator (PAG) group, a quencher group, an acid-labile group (ALG) and a polar unit (PU). The method also includes performing a baking process on the resist layer and developing the resist layer to form a patterned resist layer. The method further includes doping a portion of the material layer by using the patterned resist layer as a mask to form a doped region. In addition, the method includes removing the patterned resist layer.

Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: Methods of patterning semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a first dielectric layer over a semiconductor substrate; forming a first hard mask layer over the first dielectric layer; etching the first hard mask layer to form a first opening exposing a top surface of the first dielectric layer; performing a plasma treatment process on the top surface of the first dielectric layer and a top surface of the first hard mask layer; after performing the plasma treatment process, selectively depositing a spacer on a side surface of the first hard mask layer, the top surface of the first dielectric layer and the top surface of the first hard mask layer being free from the spacer after selectively depositing the spacer; and etching the first dielectric layer using the spacer as a mask.

Abstract: Disclosed methods employ acid generator components in an underlayer. Acid generated by the acid generator components diffuses into an overlying layer, e.g., a photoresist layer, and provides acid which chemically alters the photoresist, e.g., alters the solubility of the photoresist in a developer solution. The acid that diffuses into the overlying photoresist layer increases the concentration and the uniformity of concentration of the acid in lower portions of the photoresist. The regions of increased acid concentration within the photoresist can increase the photoresists solubility in developer solutions, thereby reducing inadequate development of the photoresist. Reducing inadequate development of the photoresist can reduce the amount of photoresist residue or scum that remains after development is complete.

Abstract: A negative tone photoresist and method for developing the negative tone photoresist is disclosed. For example, the negative tone photoresist includes a solvent, a dissolution inhibitor, and a polymer. The polymer includes a hydroxyl group. The polymer may be greater than 40 weight per cent of a total weight of the negative tone photoresist.

Abstract: Various embodiments herein provide techniques for service function chaining (SFC) in a wireless cellular network and/or an edge data network. In some embodiments, a service function path (SFP) is configured across both the wireless cellular network and the edge data network. In other embodiments, a SFP is configured in the edge data network. Other embodiments may be described and claimed.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: Described is a Logical Network Controller (LNC) operable to communicate with a User Equipment (UE) on a wireless network. The LNC may be operable to process connection request transmissions from the UE requesting a connection with an application service, such as a Mission-Critical Internet-of-Things (MC-IoT) service, to determine a Connection-specific Application Server Instance (CASI) for the application service, and to generate connection response transmissions for the UE carrying a connection-specific source IP address corresponding to the UE and a connection-specific destination IP address corresponding to the CASI.

Abstract: Systems and methods to support coexistence of multi-connectivity functions in 3GPP network and non-3GPP networks for UEs and to provide traffic routing policies and coordinate with ATSSS operation in 5GS are described. The AF subscribes to a registration-state notification event. A report is sent to the AF from the PCF or NEF. The report indicates a current registration state of a UE and is triggered when the registration state of the UE changes. The report may be sent with or without PDU session information, the former of which may be based on a determination by the AMF or the SMF. Traffic steering is enforced by the MAMS among multiple IP sessions coordinated via a single or a multiple PDU sessions in the 3GPP network.