Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).

Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.

Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

Abstract: In some embodiments, a low-resistance path between an active cell and a power supply layer in an integrated circuit device includes at least one layer of a plurality of conductive lines commonly connected to at least one conductive line through a plurality of respective conductive pillars, the at least one conductive line being in the power supply layer or intervening the active cell and the power supply layer. In some embodiments, the integrated circuit device includes a conductive layer that includes the plurality of conductive lines and additional conductive portions, where the plurality of conductive lines are isolated from the additional conductive portions.

Abstract: A touch display device for preventing light leakage is provided, including a display module, a first adhesive layer, a touch sensing film, and at least one protective layer. The display module includes an upper surface, a side surface, and a lower surface. The first adhesive layer is disposed on the upper surface of the display module and is bent and extends along the side surface to the lower surface, and the touch sensing film is disposed on the first adhesive layer. The at least one protective layer is disposed on one side of the touch sensing film relative to the side surface and the lower surface of the display module. At least one of the first adhesive layer disposed on the side surface of the display module or the protective layer is an opaque material, so the thickness of the device can be reduced.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: An antenna structure includes a patch antenna including two opposite edges, a microstrip line connected to the patch antenna, two first radiation assemblies respectively disposed on two sides of the patch antenna, two second radiation assemblies disposed under the two first radiation assemblies, a liquid crystal layer disposed between a first plane and a second plane, and a ground plane disposed under the two second radiation assemblies. The patch antenna, the microstrip line, and the two first radiation assemblies are located on the first plane, and each of the first radiation assemblies includes multiple separated first conductors. The two second radiation assemblies are located on the second plane, and each of the second radiation assemblies includes multiple separated second conductors. A projection of the two second radiation assemblies on the first plane, the two first radiation assemblies, and the two edges of the patch antenna collectively form two loops.

Abstract: A multiply accumulate circuit receives m one-bit neuron values from a first layer of a neural network system. The multiply accumulate circuit includes m non-volatile memory cells and m current sources. In addition, m current paths are defined by the m non-volatile memory cells and the m current sources collaboratively. A first current path is defined by a first non-volatile memory cell and a first current source. A first terminal of the first current source receives a first supply voltage. A second terminal of the first current source is connected with a first terminal of the first non-volatile memory cell. A second terminal of the first non-volatile memory cell is connected with an output terminal of the multiply accumulate circuit. A control terminal of the first current source receives a first one-bit neuron value.

Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by performing computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by perform computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Abstract: A movable adaptive structure for external devices has a main body and a movable element. The main body has an adapting window, an adapting terminal and a stationary portion. The adapting window is disposed on one side of the main body. The adapting terminal is disposed in the main body. The adapting terminal corresponds in position to the adapting window and thus is in communication with the outside, to adapt to an external device. The stationary portion is positioned proximate to the adapting window. The movable element has at least two positioning portions spaced apart and moves relative to the adapting window such that any one of the positioning portions is positioned at the stationary portion to change area of the adapting window. Therefore, the adaptive structure operates flexibly enough to adapt to the external device of variable dimensions.

Abstract: Disclosed is a method of acquiring input and output voltage information by employing a pulse width modulation (PWM) controller, which is in collocation with an input power processing unit, a primary inductor, a switch element, a current-sensing resistor, an output rectifier, and an output filter for converting an alternating current input power into an rectified input power and an output power, and the output power supplies an external load. A current-sensing signal is specifically disposed and applied to calculation of the input voltage and output voltage of the rectified input power when the switch element is turned on and off, respectively. Thus, no resistive voltage divider is needed, and power consumption at no load is greatly improved.

Abstract: Disclosed is an integrated PFC and PWM controller with a plurality of frequency-load curves to minimize the no-load power consumption and maximize 4-point average efficiencies. The controller selects a frequency-load curve among the plurality of frequency-load and controls the PFC stage and the PWM stage to operate in HM, BM, DCM, or CCM based on the combined result from the input voltage and the output load sense signal, fetched respectively from the input terminal of the PFC stage and the output terminal of the PWM stage. The controller has the PSU operate in HM in case of no load, and operate in BM, DCM or CCM as the load increases across the flyback out rail.

Abstract: A pump apparatus and a pump apparatus monitoring system are disclosed. The pump apparatus monitoring system includes a cloud server, a remote electronic device, a near end electronic device and a pump apparatus. The pump apparatus includes a control module and at least one parameter sensor. The parameter sensor is for sensing at least one parameter of the pump apparatus. The control module transmits the at least one parameter to the near end electronic device. The near end electronic device uploads the at least one parameter to the cloud server via a network. The remote electronic device downloads the at least one parameter from the cloud server via the network. Accordingly, staff at the remote end is able to get parameters of the pump apparatus by the remote electronic device, so as to adjust the pump apparatus.

Abstract: Disclosed is a PWM controller with programmable switching frequency for PSR/SSR flyback converter so as to maximize the performance-to-cost ratio by tailor-making the switching frequency as a non-decreasing function of the output load and the maximum switching frequency as a non-increasing function of the input voltage, leading to a plurality of programmable voltage-dependent frequency-load curves, making possible the downsizing of flyback transformer while facilitating the simultaneous compliance with DoE and CoC efficiency requirements.

Abstract: Disclosed is a PWM controller with programmable switching frequency for PSR/SSR flyback converter so as to maximize the performance-to-cost ratio by tailor-making the switching frequency as a non-decreasing function of the output load and the maximum switching frequency as a non-increasing function of the input voltage, leading to a plurality of programmable voltage-dependent frequency-load curves, making possible the downsizing of flyback transformer while facilitating the simultaneous compliance with DoE and CoC efficiency requirements.

Abstract: Disclosed is an isolated power conversion system for providing a function of isolated power conversion by converting an AC power into a DC output power, and a rectifying unit, a transformer, a switching transistor, a first pulse width modulation (PWM) controller, a second PWM controller, an output unit and a signal blocking unit are included. The signal blocking unit is employed as a connection interface between the first and second PWM controllers to provide digital signal for communication. Noise margin and stability of electrical operation are improved to avoid malfunction. Overall, the present invention greatly enhances stability of power conversion and secures quality of electrical signal.