Abstract: A multiply accumulate circuit receives m one-bit neuron values from a first layer of a neural network system. The multiply accumulate circuit includes m non-volatile memory cells and m current sources. In addition, m current paths are defined by the m non-volatile memory cells and the m current sources collaboratively. A first current path is defined by a first non-volatile memory cell and a first current source. A first terminal of the first current source receives a first supply voltage. A second terminal of the first current source is connected with a first terminal of the first non-volatile memory cell. A second terminal of the first non-volatile memory cell is connected with an output terminal of the multiply accumulate circuit. A control terminal of the first current source receives a first one-bit neuron value.

Abstract: A control method for a non-volatile memory is provided. After the non-volatile memory is enabled, a judging step is performed to judge whether the non-volatile memory enters a read mode, a program mode or an erase mode. If the judging result indicates that the non-volatile memory enters the read mode, the program mode or the erase mode, a worst threshold voltage of plural reference cells of the non-volatile memory is searched. Then, at least one of a control voltage for read action, a control voltage for program verify and a control voltage for erase verify is determined. Then, a read action, a program action or an erase action is performed on plural data cells of the non-volatile memory.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: A multiply accumulate circuit receives m one-bit neuron values from a first layer of a neural network system. The multiply accumulate circuit includes m non-volatile memory cells and m current sources. In addition, m current paths are defined by the m non-volatile memory cells and the m current sources collaboratively. A first current path is defined by a first non-volatile memory cell and a first current source. A first terminal of the first current source receives a first supply voltage. A second terminal of the first current source is connected with a first terminal of the first non-volatile memory cell. A second terminal of the first non-volatile memory cell is connected with an output terminal of the multiply accumulate circuit. A control terminal of the first current source receives a first one-bit neuron value.

Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by performing computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: A control circuit for a neural network system includes a first multiply accumulate circuit, a first neuron value storage circuit and a first processor. The first multiply accumulate circuit includes n memristive cells. The first terminals of the n memristive cells receive a supply voltage. The second terminals of the n memristive cells are connected with a first bit line. The control terminals of the n memristive cells are respectively connected with n word lines. Moreover, n neuron values of a first layer are stored in the first neuron value storage circuit. In an application phase, the first neuron value storage circuit controls the n word lines according to binary codes of the n neuron values. The first processor generates a first neuron value of a second layer.

Abstract: A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by perform computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Abstract: A movable adaptive structure for external devices has a main body and a movable element. The main body has an adapting window, an adapting terminal and a stationary portion. The adapting window is disposed on one side of the main body. The adapting terminal is disposed in the main body. The adapting terminal corresponds in position to the adapting window and thus is in communication with the outside, to adapt to an external device. The stationary portion is positioned proximate to the adapting window. The movable element has at least two positioning portions spaced apart and moves relative to the adapting window such that any one of the positioning portions is positioned at the stationary portion to change area of the adapting window. Therefore, the adaptive structure operates flexibly enough to adapt to the external device of variable dimensions.

Abstract: Disclosed is a method of acquiring input and output voltage information by employing a pulse width modulation (PWM) controller, which is in collocation with an input power processing unit, a primary inductor, a switch element, a current-sensing resistor, an output rectifier, and an output filter for converting an alternating current input power into an rectified input power and an output power, and the output power supplies an external load. A current-sensing signal is specifically disposed and applied to calculation of the input voltage and output voltage of the rectified input power when the switch element is turned on and off, respectively. Thus, no resistive voltage divider is needed, and power consumption at no load is greatly improved.

Abstract: Disclosed is an integrated PFC and PWM controller with a plurality of frequency-load curves to minimize the no-load power consumption and maximize 4-point average efficiencies. The controller selects a frequency-load curve among the plurality of frequency-load and controls the PFC stage and the PWM stage to operate in HM, BM, DCM, or CCM based on the combined result from the input voltage and the output load sense signal, fetched respectively from the input terminal of the PFC stage and the output terminal of the PWM stage. The controller has the PSU operate in HM in case of no load, and operate in BM, DCM or CCM as the load increases across the flyback out rail.

Abstract: A pump apparatus and a pump apparatus monitoring system are disclosed. The pump apparatus monitoring system includes a cloud server, a remote electronic device, a near end electronic device and a pump apparatus. The pump apparatus includes a control module and at least one parameter sensor. The parameter sensor is for sensing at least one parameter of the pump apparatus. The control module transmits the at least one parameter to the near end electronic device. The near end electronic device uploads the at least one parameter to the cloud server via a network. The remote electronic device downloads the at least one parameter from the cloud server via the network. Accordingly, staff at the remote end is able to get parameters of the pump apparatus by the remote electronic device, so as to adjust the pump apparatus.

Abstract: Disclosed is a PWM controller with programmable switching frequency for PSR/SSR flyback converter so as to maximize the performance-to-cost ratio by tailor-making the switching frequency as a non-decreasing function of the output load and the maximum switching frequency as a non-increasing function of the input voltage, leading to a plurality of programmable voltage-dependent frequency-load curves, making possible the downsizing of flyback transformer while facilitating the simultaneous compliance with DoE and CoC efficiency requirements.

Abstract: Disclosed is a PWM controller with programmable switching frequency for PSR/SSR flyback converter so as to maximize the performance-to-cost ratio by tailor-making the switching frequency as a non-decreasing function of the output load and the maximum switching frequency as a non-increasing function of the input voltage, leading to a plurality of programmable voltage-dependent frequency-load curves, making possible the downsizing of flyback transformer while facilitating the simultaneous compliance with DoE and CoC efficiency requirements.

Abstract: Disclosed is an isolated power conversion system for providing a function of isolated power conversion by converting an AC power into a DC output power, and a rectifying unit, a transformer, a switching transistor, a first pulse width modulation (PWM) controller, a second PWM controller, an output unit and a signal blocking unit are included. The signal blocking unit is employed as a connection interface between the first and second PWM controllers to provide digital signal for communication. Noise margin and stability of electrical operation are improved to avoid malfunction. Overall, the present invention greatly enhances stability of power conversion and secures quality of electrical signal.

Abstract: Disclosed is a dual-mode operation controller in collocation with an input capacitor, a flyback transformer, a first primary-side switch, a second primary-side switch, a current-sensing resistor, a primary-side voltage-sensing unit, a secondary-side rectifier, and an output capacitor as a Primary-Side Regulation (PSR) flyback converter, which is dynamically controlled to operate in two operating modes, including Quasi-Resonant-Discontinuous Conduction Mode (QR-DCM) and Continuous Conduction Mode (CCM), in accordance with a loading condition so as to convert a unregulated DC input voltage source into a regulated DC output voltage source. The dual-mode operation controller has at least 5 pins, and the flyback transformer includes a primary-side winding, a secondary-side winding, and an auxiliary winding.

Abstract: Disclosed is an integrated PFC and PWM controller with a plurality of frequency-load curves to minimize the no-load power consumption and maximize 4-point average efficiencies. The controller dynamically ushers the PFC and the PWM stage into HM, BM, DCM, or CCM on the most appropriate one among the plural frequency-load curves, cherry-picked based on the combined result from the input voltage and the output load sense signals, fetched from the input and the output terminals of the PFC and the PWM stage. All in all, the controller has the PSU operate in HM in case of no load, in BM in case of little load, in DCM in case of light load, or in CCM in case of heavy load across the flyback output rail.

Abstract: A multifunction power conversion device for dynamical detection includes an input filter unit, a transformer, a switching transistor, a driving controller, a feedback unit and an output unit. Two sensing signals from the primary and auxiliary coils of the transformer form a current sensing zero detection signal. The digital control unit of the driving controller determines if a current flowing through a secondary coil of the transformer is reduced to zero due to discharging, and further finds valley of the current of the secondary coil. The switching transistor is turned on after a preset number of the valley and then turned off by a process of current sense. Therefore, the present invention greatly reduces switching loss, increases efficiency of power conversion, and particular, enhances flexibility of application to meet actual requirements by simply updating program executed by the digital control unit.

Abstract: Disclosed is an isolated power conversion system for providing a function of isolated power conversion by converting an AC power into a DC output power, and a rectifying unit, a transformer, a switching transistor, a first pulse width modulation (PWM) controller, a second PWM controller, an output unit and a signal blocking unit are included. The signal blocking unit is employed as a connection interface between the first and second PWM controllers to provide digital signal for communication. Noise margin and stability of electrical operation are improved to avoid malfunction. Overall, the present invention greatly enhances stability of power conversion and secures quality of electrical signal.