Patents by Inventor Chitra Subramanian
Chitra Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10388578Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.Type: GrantFiled: October 27, 2017Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
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Publication number: 20190156878Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.Type: ApplicationFiled: December 12, 2018Publication date: May 23, 2019Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Thomas ANDRE, Dimitri HOUSSAMEDDINE, Syed M. ALAM, Jon SLAUGHTER, Chitra SUBRAMANIAN
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Publication number: 20190139840Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
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Patent number: 10268591Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.Type: GrantFiled: May 22, 2018Date of Patent: April 23, 2019Assignee: Everspin Technologies Inc.Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian, Javed S. Barkatullah
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Patent number: 10269405Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.Type: GrantFiled: May 25, 2017Date of Patent: April 23, 2019Assignee: Everspin Technologies, Inc.Inventors: Thomas Andre, Dimitri Houssameddine, Syed M. Alam, Jon Slaughter, Chitra Subramanian
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Publication number: 20190103327Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.Type: ApplicationFiled: October 2, 2017Publication date: April 4, 2019Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
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Publication number: 20190103328Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.Type: ApplicationFiled: October 27, 2017Publication date: April 4, 2019Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
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Patent number: 10220046Abstract: Provided herein are compositions and methods for the treatment of diseases, such as hyperproliferative diseases, employing compounds formulated for pharmaceutical and research use via nanoparticles.Type: GrantFiled: July 14, 2015Date of Patent: March 5, 2019Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Anna Schwendeman, Mark Cohen, Chitra Subramanian, Rui Kuai, Dan Li, Peter White, James Moon
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Publication number: 20180342276Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.Type: ApplicationFiled: June 5, 2018Publication date: November 29, 2018Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Syed M. Alam, Chitra Subramanian
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Publication number: 20180267899Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.Type: ApplicationFiled: May 22, 2018Publication date: September 20, 2018Applicant: Everspin Technologies, Inc.Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian, Javed S. Barkatullah
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Patent number: 9990300Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.Type: GrantFiled: April 28, 2016Date of Patent: June 5, 2018Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian, Javed S. Barkatullah
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Patent number: 9972373Abstract: An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.Type: GrantFiled: June 29, 2017Date of Patent: May 15, 2018Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian
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Publication number: 20170315920Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian, Javed S. Barkatullah
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Publication number: 20170301384Abstract: An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.Type: ApplicationFiled: June 29, 2017Publication date: October 19, 2017Applicant: Everspin Technologies, Inc.Inventors: Thomas ANDRE, Syed M. ALAM, Chitra SUBRAMANIAN
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Publication number: 20170263300Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.Type: ApplicationFiled: May 25, 2017Publication date: September 14, 2017Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Thomas ANDRE, Dimitri HOUSSAMEDDINE, Syed M. ALAM, Jon SLAUGHTER, Chitra SUBRAMANIAN
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Patent number: 9697880Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.Type: GrantFiled: June 25, 2016Date of Patent: July 4, 2017Assignee: Everspin Technologies, Inc.Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian
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Patent number: 9679627Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.Type: GrantFiled: September 30, 2014Date of Patent: June 13, 2017Assignee: Everspin Technologies, Inc.Inventors: Thomas Andre, Dimitri Houssameddine, Syed M. Alam, Jon Slaughter, Chitra Subramanian
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Publication number: 20170157149Abstract: Provided herein are compositions and methods for the treatment of diseases, such as hyperproliferative diseases, employing compounds formulated for pharmaceutical and research use via nanoparticles.Type: ApplicationFiled: July 14, 2015Publication date: June 8, 2017Inventors: Anna SCHWENDEMAN, Mark COHEN, Chitra SUBRAMANIAN, Rui KUAI, Dan LI, Peter WHITE, James MOON
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Patent number: 9502093Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits using an additional offset current, and compare the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation.Type: GrantFiled: May 27, 2016Date of Patent: November 22, 2016Assignee: Everspin Technologies, Inc.Inventors: Syed M. Alam, Thomas Andre, Matthew R. Croft, Chitra Subramanian, Halbert Lin
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Publication number: 20160307615Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.Type: ApplicationFiled: June 25, 2016Publication date: October 20, 2016Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian