Patents by Inventor Chiu-Ming Chou

Chiu-Ming Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8836146
    Abstract: A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: September 16, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Chien-Kang Chou, Chiu-Ming Chou, Li-Ren Lin, Hsin-Jung Lo
  • Patent number: 8674507
    Abstract: A chip structure comprising a substrate, a plurality of wire bonding pads and a plurality of solder pads is provided. Gold bumps or gold pads can be formed on the wire bonding pads while solder bumps can be formed on the solder pads concurrently. Alternatively, both wire bonding pads and solder pads can be formed of the same metal stack.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: March 18, 2014
    Assignee: Megit Acquisition Corp.
    Inventors: Chien-Kang Chou, Chiu-Ming Chou, Li-Ren Lin, Chu-Fu Lin
  • Patent number: 8592977
    Abstract: A method for fabricating an integrated circuit (IC) chip includes providing a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, next forming a first titanium-containing layer over the pad exposed by the opening, next performing an annealing process by heating the titanium-containing layer at a temperature of between 300 and 410° C. for a time of between 20 and 150 minutes in a nitrogen ambient with a nitrogen purity of great than 99%, next forming a second titanium-containing layer on the first titanium-containing layer, and then forming a metal layer on the second titanium-containing layer.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 26, 2013
    Assignee: Megit Acquisition Corp.
    Inventors: Chiu-Ming Chou, Jin-Yuan Lee
  • Patent number: 8581404
    Abstract: A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first metal layer exposed by an opening in said first mask layer. Said first mask layer is removed. A second mask layer is deposited over said second metal layer. A third metal layer is deposited over said second metal layer exposed by an opening in said second mask layer. Said second mask layer is removed. Said first metal layer not covered by said second metal layer is removed.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: November 12, 2013
    Assignee: Megit Acquistion Corp.
    Inventors: Chiu-Ming Chou, Mou-Shiung Lin
  • Patent number: 8552559
    Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 8, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Patent number: 8519552
    Abstract: A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: August 27, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou
  • Patent number: 8426958
    Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: April 23, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen, Chiu-Ming Chou
  • Patent number: 8399989
    Abstract: A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: March 19, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
  • Patent number: 8362588
    Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: January 29, 2013
    Assignee: Megica Corporation
    Inventors: Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee
  • Patent number: 8344524
    Abstract: This invention provides a wire bonding method, comprising providing an integrated circuit (IC) die having thereon a passivation layer and a plurality of first bonding pads exposed by respective openings in the passivation layer; forming a polymer layer on the passivation layer; forming an adhesive/barrier layer on the polymer layer; forming a metal pad layer on the adhesive/barrier layer; bonding a wire onto the metal pad layer to form a ball bond thereon; and after forming the ball bond on the metal pad layer, running the wire so as to contact the wire with a second bonding pad and forming a wedge bond thereto.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: January 1, 2013
    Assignee: Megica Corporation
    Inventors: Chiu-Ming Chou, Shih-Hsiung Lin, Mou-Shiung Lin, Hsin-Jung Lo
  • Patent number: 8319354
    Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: November 27, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin
  • Patent number: 8304907
    Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: November 6, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Patent number: 8304766
    Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: November 6, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Huei-Mei Yen, Hsin-Jung Lo, Chiu-Ming Chou, Ke-Hung Chen
  • Patent number: 8242601
    Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: August 14, 2012
    Assignee: Megica Corporation
    Inventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin
  • Patent number: 8198729
    Abstract: A semiconductor chip or wafer includes a passivation layer, a pad and a bump. The pad is exposed by an opening in the passivation layer. The bump is connected to the pad, wherein the area of the connection between the pad and the bump is larger than 30,000 ?m2.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: June 12, 2012
    Assignee: Megica Corporation
    Inventors: Chiu-Ming Chou, Chien-Kang Chou, Mou-Shiung Lin
  • Patent number: 8168527
    Abstract: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: May 1, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou
  • Patent number: 8159074
    Abstract: A semiconductor chip includes first, second and third metal interconnects and an insulating layer over a semiconductor substrate. First, second and third openings in the insulating layer are over first, second and third contact points of the first, second and third metal interconnects, respectively. A fourth metal interconnect over the insulating layer connects the first and second contact points. The fourth metal interconnect includes a first metal layer and a second metal layer. The first metal layer is under but not at a sidewall of the second metal layer. The semiconductor chip includes a metal bump connected to the third contact point through the third opening, and a dielectric layer over the fourth metal interconnect and the insulating layer. No opening is in the dielectric layer on the fourth metal interconnect, and the metal bump has a top higher than a top surface of the dielectric layer.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: April 17, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo
  • Patent number: 8148822
    Abstract: A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: April 3, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
  • Patent number: 8120181
    Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: February 21, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Publication number: 20110291272
    Abstract: A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Applicant: MEGICA CORPORATION
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou