Patents by Inventor Chiu-Ming Chou
Chiu-Ming Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8120181Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.Type: GrantFiled: July 30, 2008Date of Patent: February 21, 2012Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Publication number: 20110291272Abstract: A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.Type: ApplicationFiled: August 10, 2011Publication date: December 1, 2011Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Chiu-Ming Chou
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Publication number: 20110266669Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer.Type: ApplicationFiled: July 12, 2011Publication date: November 3, 2011Applicant: MEGICA CORPORATIONInventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin, Hsin-Jung Lo
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Publication number: 20110241183Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.Type: ApplicationFiled: June 13, 2011Publication date: October 6, 2011Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen, Chiu-Ming Chou
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Publication number: 20110233776Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.Type: ApplicationFiled: June 13, 2011Publication date: September 29, 2011Applicant: MEGICA CORPORATIONInventors: Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee
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Patent number: 8022544Abstract: A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.Type: GrantFiled: July 11, 2005Date of Patent: September 20, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou
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Patent number: 8018060Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.Type: GrantFiled: January 16, 2008Date of Patent: September 13, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Publication number: 20110215469Abstract: A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.Type: ApplicationFiled: May 16, 2011Publication date: September 8, 2011Applicant: Megica CorporationInventors: Hsin-Jung Lo, Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Patent number: 8013449Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: June 20, 2008Date of Patent: September 6, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Patent number: 8008775Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.Type: GrantFiled: December 20, 2004Date of Patent: August 30, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Publication number: 20110204510Abstract: A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicant: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo
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Patent number: 8004092Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.Type: GrantFiled: June 4, 2008Date of Patent: August 23, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin
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Publication number: 20110198589Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.Type: ApplicationFiled: April 26, 2011Publication date: August 18, 2011Applicant: Megica CorporationInventors: Mou-Shiung Lin, Huei-Mei Yen, Chiu-Ming Chou, Hsin-Jung Lo, Ke-Hung Chen
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Patent number: 7985653Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.Type: GrantFiled: November 24, 2008Date of Patent: July 26, 2011Assignee: Megica CorporationInventors: Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee
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Patent number: 7977803Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.Type: GrantFiled: November 7, 2010Date of Patent: July 12, 2011Assignee: Megica CorporationInventors: Nick Kuo, Chiu-Ming Chou, Chien-Kang Chou, Chu-Fu Lin
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Patent number: 7973401Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.Type: GrantFiled: November 12, 2008Date of Patent: July 5, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen, Chiu-Ming Chou
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Patent number: 7964973Abstract: A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.Type: GrantFiled: September 1, 2008Date of Patent: June 21, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo
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Patent number: 7960269Abstract: A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.Type: GrantFiled: July 24, 2006Date of Patent: June 14, 2011Assignee: Megica CorporationInventors: Hsin-Jung Lo, Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
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Patent number: 7947978Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.Type: GrantFiled: December 5, 2006Date of Patent: May 24, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Huei-Mei Yen, Chiu-Ming Chou, Hsin-Jung Lo, Ke-Hung Chen
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Patent number: 7919412Abstract: A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees Celsius. Alternatively, the temperature profile may comprises a period of time with a temperature higher than 320 degree Celsius, wherein the period of time is shorter than 45 minutes.Type: GrantFiled: November 19, 2008Date of Patent: April 5, 2011Assignee: Megica CorporationInventors: Ying-Chih Chen, Mou-Shiung Lin, Chiu-Ming Chou