Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A hard mask (HM) layer is formed over a dielectric layer over a substrate. A plurality of mandrels are formed over the HM layer. A spacer layer including a plurality of trenches between the mandrels is formed over the HM layer and the mandrels. A first and a second portion of the trenches is filled by a first and a second block material, respectively. A third portion of the trenches is free from filled by these block materials. At least a first opening is formed in the spacer layer. At least a second opening is formed by removing a portion of the mandrels. The HM layer is etched through the first and the second openings. The dielectric layer is patterned. A plurality of conductive lines are formed in the patterned dielectric layer.

Abstract: A method of modifying a layout for an integrated circuit (IC) includes: selecting, in the layout, a circuit region to be scaled; setting a fixed area including a fixed feature in the selected circuit region; and scaling the selected circuit region, without scaling the fixed area including the fixed feature, to obtain a modified layout for the IC.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a metallization layer. The metallization layer is disposed over the substrate. The metallization layer includes a first signal line, a second signal line, and a third signal line, wherein the first signal line, the second signal line, and the third signal line are arranged in a first row between a power rail and a ground rail parallel to the power rail. A first distance between the first signal line and the second signal line is different from a second distance between the second signal line and the third signal line. A method for manufacturing a semiconductor structure is also provided.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: A method includes assigning a default voltage value to a net in an integrated circuit (IC) schematic, generating a simulation voltage value of the net by performing a circuit simulation on the net using the assigned default voltage value, and modifying the IC schematic to include a voltage value associated with the net. The voltage value associated with the net and included in the modified IC schematic is based on a comparison between the assigned default voltage value and the simulation voltage value of the net.

Abstract: A vertical cavity surface emitting laser (VCSEL) including a first ohmic contact to the substrate formed on an upper surface of the device, instead of the conventional substrate bottom-side contact. The VCSEL is formed to include a hole made through the first distributed Bragg reflector (DBR) and into the material of the substrate itself. A metal layer is deposited at the bottom of the hole to contact the substrate, where the deposited metal layer creates a high quality ohmic contact by not also contacting the inner sidewalls of the hole (i.e., no “stringers” are formed within the hole).

Abstract: A method of making a semiconductor device includes determining a first scaling factor for a first region of a first device layout, wherein the first region comprises a first plurality of conductive patterns. The method further includes determining a second scaling factor for a second region of the first device layout, wherein the second region comprises a second plurality of conductive patterns, and the first device layout comprises an interconnect pattern extending from the first region to the second region. The method further includes generating a second device layout. Generating the second device layout includes adjusting the interconnect pattern based on the first scaling factor and the second scaling factor.

Abstract: A method of making a semiconductor device includes receiving a first layout of a device in a first technology node, wherein the first layout comprises a plurality of first conductive patterns spaced along a first direction and a plurality of first interconnect patterns connecting at least two of the plurality of first conductive patterns. The method includes identifying a plurality of second conductive patterns from the plurality of first conductive patterns according to a second technology node different from the first technology node. The method includes determining a scaling factor for the first layout in the first direction based on the plurality of first conductive patterns and the plurality of second conductive patterns. The method includes adjusting the plurality of first interconnect patterns along the first direction using the scaling factor to determine a plurality of second interconnect patterns connecting at least two of the plurality of second conductive patterns.

Abstract: A method for forming a metal contact in a deep hole in a workpiece. A first hole is formed that extends from the upper surface of the workpiece to a substrate at the bottom of the hole. The hole is then filled with photoresist. Next, a photolithographic process is performed to create a second hole within the photoresist and to expose the substrate; and a wet etch is performed to remove a portion of the substrate. A layer of contact metal is then deposited on the surface of the photoresist. In the second hole, the metal layer is formed on the exposed surface of the substrate and on discontinuous portions of the photoresist on the sidewalls. A liftoff process is then used to remove the photoresist and the metal deposited on the photoresist while leaving the metal at the bottom of the second hole in contact with the substrate.

Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.

Abstract: A display device includes a display panel, a light source module and a control unit. The display panel includes plural display areas. The light source module includes plural light source units. The light source units are configured to output plural light beams to illuminate the display areas of the display panel. The control unit is coupled to the light source module and configured to receive a frame data. The frame data includes plural subframe data, and the subframe data are displayed on the display areas. The control unit is further configured to control a first light source unit of the light source units to adjust a brightness corresponding to a first color of a first light beam of the light beams according to a ratio of the first color. The ratio of the first color is related to a first subframe data of the subframe data.

Abstract: A method includes assigning a default voltage value to a net in an integrated circuit (IC) schematic, generating a simulation voltage value of the net by performing a circuit simulation on the net using the assigned default voltage value, and modifying the IC schematic to include a voltage value associated with the net. The voltage value associated with the net and included in the modified IC schematic is based on a comparison between the assigned default voltage value and the simulation voltage value of the net.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: A method includes assigning a default voltage value of a voltage domain in an integrated circuit (IC) schematic to a net in the voltage domain, generating a simulation voltage value of the net by performing a circuit simulation on the net, and modifying the IC schematic to include a voltage value associated with the net, based on the simulation voltage value of the net.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: Methods for compensating for bow in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming an adhesion layer on the backside of the wafer, and forming a stress compensation layer on the adhesion layer.

Abstract: A method of making a semiconductor device includes receiving a first layout of a device in a first technology node, wherein the first layout comprises a plurality of first conductive patterns spaced along a first direction and a plurality of first interconnect patterns connecting at least two of the plurality of first conductive patterns. The method includes identifying a plurality of second conductive patterns from the plurality of first conductive patterns according to a second technology node different from the first technology node. The method includes determining a scaling factor for the first layout in the first direction based on the plurality of first conductive patterns and the plurality of second conductive patterns. The method includes adjusting the plurality of first interconnect patterns along the first direction using the scaling factor to determine a plurality of second interconnect patterns connecting at least two of the plurality of second conductive patterns.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: A method of modifying an integrated circuit (IC) design layout is provided. The method includes receiving a first IC design layout having first gate layout patterns and first interconnect layout patterns. Second gate layout patterns for a second IC design layout are then obtained from the first gate layout patterns according to a set of design rules associated with a technology node different from that of the first IC design layout. After determining scaling factors for the first IC design layout based on the first gate layout patterns and the second gate layout patterns such that each scaling factor corresponds to one of at least one shrinkable region and at least one non-shrinkable region in the first IC design layout, the first interconnect layout patterns are adjusted using the scaling factors to determine second interconnect layout patterns for the second IC design layout.

Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.