Abstract: A liquid crystal display includes a pixel electrode including a first subpixel electrode and a second subpixel electrode spaced apart with a gap therebetween, a common electrode facing the pixel electrode, and a liquid crystal layer formed between the pixel electrode and the common electrode and including a plurality of liquid crystal molecules. The first and second subpixel electrodes include a plurality of branches, and each of the first and second subpixel electrodes includes a plurality of subregions. The branches extend in different directions in different subregions.

Abstract: A liquid crystal display according to an embodiment of the present invention includes: first and second substrates opposed to each other; a liquid crystal layer including liquid crystal molecules interposed between the first and second substrates; a gate line formed on the first substrate and transmitting a gate signal; first and second data lines formed on the first substrate and transmitting first and second data voltages having different polarities; a first switching element connected to the gate line and the first data line; a second switching element connected to the gate line and the second data line; and first and second pixel electrodes that are connected to the first and second switching elements, respectively, and separated from each other, wherein the liquid crystal layer has positive dielectric anisotropy.

Abstract: A display apparatus includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel of the plurality of pixels comprises a switching device coupled to a corresponding gate line of the plurality of gate lines and to a corresponding data line of the plurality of data lines, a micro-electro-mechanical system coupled to an output electrode of the switching device, and a control device coupled to the output electrode of the switching device. The control device comprises a storage capacitor coupled to the output electrode of the switching device and a coupling capacitor coupled to the output electrode of the switching device, the storage capacitor connected in parallel with the coupling capacitor. The output electrode of the switching device, the storage capacitor, the coupling capacitor, and a first electrode of the micro-electro-mechanical system are all directly connected to each other.

Abstract: In a touch substrate and a display apparatus, the touch substrate includes a first electrode, a second electrode, a first touch electrode and a blocking layer. The first electrode includes an opaque conductive material and extends along a first direction. The second electrode includes the opaque conductive material, extends along a second direction crossing the first direction, and has a gap through which the first electrode extends. The first touch electrode is formed on the first electrode and is electrically connected to the first electrode. The blocking layer overlaps the first and second electrodes.

Abstract: A pixel, a display device having the same, and a thin film transistor (TFT) substrate for the display device are disclosed. In one aspect, the pixel includes an emitter configured to emit light based at least in part on a driving current. The pixel also includes a driving transistor including an active layer, a first electrode electrically connected to a first end portion of the active layer, a second electrode electrically connected to a second end portion of the active layer, a first gate electrode configured to receive a data voltage from a data driver so as to form a channel in the active layer, and a second gate electrode configured to receive a bias voltage from a voltage source, wherein the channel is configured to adjust the driving current.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract: A display device includes pixels arranged in a matrix form, gate lines extending in a first direction; data lines extending in a second direction, first and second unit pixel columns, each defined by adjacent data lines and the pixels connected thereto, first and second channels which transmit data signals to each of the first and second unit pixel columns, and a line selector which connects the first and second channels to the data lines and provides data voltages to the data lines in response to control signals, where a pixel connected to a first gate line is connected to a data line at a side thereof, a pixel connected to a second gate line is connected to a data line at the other side thereof, and each of the first and second channels is connected to a data line of each of the first and second unit pixel columns.

Abstract: The present invention relates to a display apparatus with pixels, wherein each pixel includes a switching device, a micro-electro-mechanical system (MEMS), and a gray scale control device. The switching device can be connected to a gate line and a data line to output a corresponding data signal in response to a gate signal. The MEMS may be connected to an output electrode of the switching device to transmit or block light in response to the corresponding data signal. The gray scale control device may be coupled to the output electrode of the switching device to control a time interval during which the corresponding data signal is applied to the MEMS. Accordingly, each pixel may display a desired gray scale.

Abstract: A display apparatus includes a panel module displaying a 2-dimensional (2D) image or a 3-dimensional (3D) stereoscopic image, a lens panel disposed over the panel module and including a first substrate, a second substrate and a liquid crystal layer disposed between the first substrate and the second substrate, the first substrate including a plurality of first electrodes, a plurality of floating electrodes and a plurality of second electrodes, the floating electrodes partially overlapping with the first electrodes and being electrically floated, the second electrodes partially overlapping with the floating electrodes, and a light source module supplying light to the panel module.

Abstract: A display apparatus is disclosed. The display apparatus includes a display panel and a gate driving circuit. The display panel includes a base substrate and a switching transistor. The base substrate includes a display area displaying an image and a peripheral area surrounding the display area. The switching transistor includes a first gate electrode disposed on the display area, a first channel disposed on the first gate electrode, and a first source electrode and a first drain electrode being spaced apart from each other with respect to the first channel. The gate driving circuit includes a driving transistor integrated on the peripheral area of the display panel applying gate signals to the display panel.

Abstract: A gate driver includes a stage including an input unit including a first transistor diode-connected to a first input terminal of the stage through a first node and biased by a first input signal of the first input terminal, an output unit including a second transistor including a gate electrode coupled to the first node, a first electrode coupled to a clock input terminal, and a second electrode coupled to a first output terminal of the stage, a capacitor coupled between the gate electrode and the second electrode of the second transistor, and a noise remover including a third transistor including a gate electrode coupled to a second node, a first electrode coupled to the first node, and a second electrode coupled to a first voltage input terminal of the stage which receives a first voltage.

Abstract: A display panel includes a gate line, a gate electrode, a planarization layer, a gate insulation layer, an active layer, a data line, a source electrode, a drain electrode, and a pixel electrode. The gate electrode extends from the gate line. The planarization layer covers the gate line and the gate electrode to have an opening exposing a portion of the gate electrode formed therethrough. The gate insulation layer covers a portion of the gate electrode exposed by the opening and the planarization layer. The active layer is formed on the gate insulation layer and corresponds to the gate electrode. The data line is formed. The source electrode extends from the data line to cover a portion of the opening. The drain electrode is spaced apart from the source electrode and covers a portion of the opening. The pixel electrode is connected to the drain electrode.

Abstract: A display substrate includes a base substrate including a display area in which signal lines and pixels are arranged and a peripheral area surrounding the display area, pads disposed in the peripheral area and receiving an electrical signal, fan-out lines connecting the pads and the signal lines, and static electricity breakup circuits comprising a breakup line that crosses the fan-out lines, and static electricity prevention circuits respectively connected to the fan-out lines. Parts of the static electricity prevention circuits are connected to adjacent fan-out lines and are commonly connected to the one of the breakup lines through a common contact part.

Abstract: A gate driver and a display device are disclosed. In one aspect, the gate driver includes a plurality of stages connected in cascade. Each of the stages includes an input unit, an output unit and a carry signal generator. The input unit connects a first input terminal and a first node and includes a first input transistor and a second input transistor. The output unit connects the first node and a first output terminal and includes an output transistor and an output capacitor. The carry signal generator connects a clock terminal and a second output terminal. An output terminal of the first input transistor and an input terminal of the second input terminal are connected to a second node. The input unit further includes a diode-connected transistor applying a carry signal from the first output terminal to the second node.

Abstract: A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.

Abstract: A gate driver includes a plurality of stages connected to each other in a cascade manner, where each of the stages includes an input unit which connects a first input terminal and a first node and includes a first input transistor and a second input transistor, where an output terminal of the first input transistor and an input terminal of the second input transistor are connected to a second node, and the input unit further includes a storage capacitor which connects the first input terminal and the second node.

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: The display device includes a substrate, a thin film transistor (TFT), which includes a gate electrode, a semiconductor layer, and source and drain electrodes, on the substrate member, a passivation layer on the TFT and having an opening to expose a portion of the drain electrode, and a pixel electrode directly on the drain electrode and only within the opening.

Abstract: A display device includes: an insulation substrate; a plurality of gate lines on the insulation substrate and divided into a first group and a second group; a plurality of data lines insulated from and intersecting the gate lines; a gate driver which applies a gate-on voltage to the gate lines and operates in one of a first mode and a second mode; and a data driver which applies a data voltage to the data lines, where the first group and the second group of the gate lines are applied with the gate-on voltage when the gate driver is in the first mode, and where the first group of the gate lines is applied with the gate-on voltage and the second group of the gate lines is in an off state when the gate driver is in the second mode.