Abstract: A stage circuit includes an output part configured to supply a carry signal to a first output terminal and a scan signal to a second output terminal, in response to a voltage of a first node, a voltage of a second node, and a first clock signal being supplied to a first input terminal, a controller configured to control the voltage of the second node in response to the first clock signal being supplied to the first input terminal, a pull-up part configured to control the voltage of the first node in response to a carry signal of a previous stage being supplied to a second input terminal, and a pull-down part configured to control the voltage of the first node in response to the voltage of the second node and the carry signal of a next stage being supplied to a third input terminal.

Abstract: An organic light emitting display device includes a plurality of pixels. A pixel on an ith horizontal line includes a first transistor coupled between a first power source and a first node and having a gate electrode coupled to a second node. An organic light emitting diode is coupled between the first node and a second power source. A second transistor is coupled between the second and third nodes and is turned on when a first scan signal is supplied to an ith first scan line. A third transistor is coupled between the third and first nodes. A first capacitor is coupled between an ith control line and the second node. A second capacitor is coupled between the third node and a data line. The pixels are simultaneously driven during first, second, and third periods of a frame period and sequentially driven during a fourth period of the frame period.

Abstract: A stage circuit includes an output circuit configured to supply, to a first output terminal, a first clock signal supplied to a second input terminal or to supply a voltage of a second power source supplied to a second power input terminal, in response to voltages of a first node and a second node, an input circuit configured to control voltages of a third node and a fourth node in response to a shift pulse or a gate start pulse supplied to a first input terminal, a third clock signal supplied to a third input terminal, and a fourth clock signal supplied to a fourth input terminal, and a first driver configured to control the voltages of the first and second nodes in response to both the third clock signal and the voltages of the third and fourth nodes.

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: A display device includes: a first substrate including a touch region for sensing a touch and a peripheral area surrounding the touch region; a second substrate facing the first substrate; thin film transistors positioned on the first substrate; pixel electrodes connected to the thin film transistors; common electrodes arranged to transmit a common voltage; sensing wires connected to the common electrodes and arranged to transmit a detection signal for sensing a touch; and a transparent electrode layer positioned on a first surface of the second substrate, the transparent electrode layer having a portion overlapping the peripheral area, and having at least one opening positioned over the touch region.

Abstract: There is provided a display device including a display including a first pixel connected to a first data line and a second pixel connected to a second data line, a data signal generator configured to generate an output signal, and a signal divider configured to divide the output signal, to generate a first data signal and a second data signal, and to apply the first data signal and the second data signal to the first data line and the second data line, respectively, wherein the data signal generator is configured to generate the output signal based on a coupling effect of a first parasitic capacitor formed between the first data line and the second data line and a coupling effect of a parasitic capacitor of a data line formed by the first data line and second data line.

Abstract: A display apparatus includes a plurality of pixels. Each pixel includes a first capacitor connected between a first voltage line receiving a driving signal and a first node; a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal, and a second electrode connected to a second node; an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal; a second capacitor connected between an m-th data line and the second node; a second transistor comprising a control electrode connected to an n-th gate line, a first electrode connected to the first node, and a second electrode connected to the second node; and a third transistor comprising a control electrode connected to an n-th scan line, a first electrode connected to the first voltage line, and a second electrode connected to the second node.

Abstract: A gate driver includes a plurality of stage circuits to output a clock signal from the outside as gate signals. A jth stage circuit includes an input unit to charge a first node at an initial voltage when a first input signal is input to a first input terminal, a buffer unit to output the clock signal as a gate signal to an output terminal when the initial voltage is supplied to the first node, a holding unit to maintain the first node at a reset power source level when the clock signal is supplied to the holding unit, and an inverter unit to supply the clock signal or the reset power source to the holding unit. The input unit maintains the first node at a second input signal input voltage to a second input terminal when a third input signal is input to a third input terminal.

Abstract: A pixel includes first to fourth transistors and a driving transistor. The first transistor is connected between a data line and a first node and has a gate electrode to receive a scan signal. The driving transistor is connected between the first node and a second node and has a gate electrode connected to a third node. The second transistor is connected between the second and third nodes and has a gate electrode to receive the scan signal. The third transistor is connected between first power and the first node and has a gate electrode to receive an emission signal. The fourth transistor is connected between the first and second nodes and has a gate electrode to receive an initialization signal. An organic light emitting diode is connected between the second node and second power. A storage capacitor is connected between the first power and third node.

Abstract: A display panel driver drives pixels based on first power having at least three voltage levels, second power having a constant voltage, and third power having two voltage levels. Each pixel includes a first transistor connected between first and second nodes and including a gate electrode to receive a scan signal, a second transistor connected between the second node and a third node in series with the first transistor and including a gate electrode to receive the third power, and a driving transistor connected between a source of the first power and the third node and including a gate electrode connected to the first electrode to control a driving current for an organic light emitting diode. A first capacitor is connected between a source of the third power and the first node, and a second capacitor is connected between the second node and one of the data lines.

Abstract: A pixel for a display panel includes first and second transistors, first and second capacitors, and an organic light emitting diode. The first transistor has a gate electrode connected to a first node, a first electrode connected to a first power source, and a second electrode connected to a second node. The second transistor has a gate electrode connected to a scan line, a first electrode connected to the first node, and a second electrode connected to the second node. The organic light emitting diode has a first electrode connected to the second node and a second electrode connected to a second power source. The first capacitor has a first electrode connected to a third power source and a second electrode connected to the first node. The second capacitor has a first electrode connected to a data line and a second electrode connected to the second node.

Abstract: A pixel including an organic light emitting diode; a first transistor for controlling the amount of current flowing from a first driving power source to a second driving power source via the organic light emitting diode, corresponding to a voltage of a first node; a second transistor coupled between the first node and a second node, the second transistor being turned on when a scan signal is supplied to an ith (i is a natural number) scan line; a third transistor coupled between the second node and an anode electrode of the organic light emitting diode; a first capacitor coupled between a data line and the second node; and a fourth transistor coupled between an initialization power source and the anode electrode of the organic light emitting diode. The fourth transistor is turned on in response to a first control signal being supplied to a first control line.

Abstract: A display apparatus includes a plurality of pixels. Each pixel includes a first capacitor connected between a first voltage line receiving a driving signal and a first node; a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal, and a second electrode connected to a second node; an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal; a second capacitor connected between an m-th data line and the second node; a second transistor comprising a control electrode connected to an n-th gate line, a first electrode connected to the first node, and a second electrode connected to the second node; and a third transistor comprising a control electrode connected to an n-th scan line, a first electrode connected to the first voltage line, and a second electrode connected to the second node.

Abstract: A pixel includes first through fourth transistors and storage capacitor. The first transistor controls an amount of current flowing from a first driving power source to a second driving power source, via an organic light-emitting diode, based on a voltage of a first node. The second transistor is coupled between a first electrode of the first transistor and the first node, and is turned on when a scan signal is supplied to a scan line. The third transistor is coupled between a second electrode of the first transistor and a reference power source, and is turned on when the scan signal is supplied. The fourth transistor is coupled between an anode electrode of the organic light-emitting diode and a data line, and is turned on when the scan signal is supplied. The storage capacitor is coupled between the first node and the anode electrode of the organic light-emitting diode.

Abstract: A pixel includes a plurality of transistors, a storage capacitor, and an organic light emitting diode. A first transistor controls the amount of current from a first driving power source to the organic light emitting diode based on a data voltage. A second transistor is connected to a data line and is turned on based on a scan signal. A third transistor coupled to the first transistor and is turned on based on the scan signal. A first stabilizing transistor is coupled to the third transistor or between the first and third transistors and is turned off when the third transistor is turned off.

Abstract: A pixel includes: an organic light emitting diode including a cathode electrode connected to a second power source; a first transistor including a first electrode connected to a first power source, and to control an amount of current flowing from the first power source to the second power source via the organic light emitting diode in response to a data signal; a plurality of second transistors connected in series between a gate electrode of the first transistor and an initialization power source, and to be turned on when a scan signal is supplied to an i?1-th (i is a natural number) scan line; and a first capacitor connected between a voltage source and a first node, the first node being between the plurality of second transistors.

Abstract: An OLED display is disclosed. A plurality of signal lines are formed over a substrate, and a plurality of pixels are formed over the substrate in a matrix form and electrically connected to corresponding signal lines. The signal lines include a plurality of scan lines configured to transmit a scan signal, a plurality of initialization lines configured to transmit an initialization signal, and a plurality of data lines configured to transmit a data signal. An n-th row pixel includes a switching thin film transistor (TFT) electrically connected to an n-th row scan line and a corresponding data line among the data lines. A driving TFT is electrically connected to a drain of the switching TFT, an OLED is electrically connected to a drain of the driving TFT, and an initialization TFT is configured to be turned on based on an initialization signal transmitted via an n-th row initialization line.

Abstract: A display substrate includes a base substrate including a display area in which signal lines and pixels are arranged and a peripheral area surrounding the display area, pads disposed in the peripheral area and receiving an electrical signal, fan-out lines connecting the pads and the signal lines, and static electricity breakup circuits comprising a breakup line that crosses the fan-out lines, and static electricity prevention circuits respectively connected to the fan-out lines. Parts of the static electricity prevention circuits are connected to adjacent fan-out lines and are commonly connected to the one of the breakup lines through a common contact part.

Abstract: A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.

Abstract: A display device includes pixels arranged in a matrix form, gate lines extending in a first direction; data lines extending in a second direction, first and second unit pixel columns, each defined by adjacent data lines and the pixels connected thereto, first and second channels which transmit data signals to each of the first and second unit pixel columns, and a line selector which connects the first and second channels to the data lines and provides data voltages to the data lines in response to control signals, where a pixel connected to a first gate line is connected to a data line at a side thereof, a pixel connected to a second gate line is connected to a data line at the other side thereof, and each of the first and second channels is connected to a data line of each of the first and second unit pixel columns.