Abstract: A display panel includes a display area including a plurality of pixels, and a peripheral area defining a non-display area. The display area includes a first light blocking member including a plurality of first openings, and the peripheral area includes a second light blocking member including a plurality of second openings.

Abstract: A liquid crystal display includes a first gate line; a common voltage line separated from the first gate line; a data line insulated from and crossing the first gate line and the common voltage line; a first switching element connected to the first gate line and the data line; a second switching element connected to the first gate line and the data line; a first liquid crystal capacitor connected to the first switching element; a second liquid crystal capacitor connected to the second switching element; a third switching element connected to the first switching element; an assistance capacitor connected to the third switching element and the common voltage line; and a shielding electrode extending in the same direction as the first gate line and connected to the first switching element.

Abstract: A mother substrate includes a display substrate cell defined by a scribe line, the display substrate cell including a plurality of gate lines, a gate circuit part driving the gate lines, and a gate pad part connected to the gate circuit part, a gate test pad part in a peripheral area surrounding the display substrate cell, the gate test pad part being configured to receive a gate test signal, a gate test line part connecting the gate test pad part and the gate pad part, and a switching part connected to the gate test line part and configured to control turning on and turning off of the gate test line part.

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract: An array substrate includes a first pixel electrode and a second pixel electrode. The first pixel electrode includes first branch electrode portions and second branch electrode portions. The first branch electrode portions are disposed in a first area of a unit pixel area and are substantially parallel to a first side of the unit pixel area. The second branch electrode portions are disposed in a second area of the unit pixel area and are substantially parallel to a second side of the unit pixel area. The second pixel electrode includes third branch electrode portions disposed between the first branch electrode portions and fourth branch electrode portions disposed between the second branch electrode portions.

Abstract: A display substrate includes thin film transistors, first common voltage lines, and second common voltage lines. Each thin film transistor includes a gate electrode, a source electrode, and an annulus-shaped drain electrode. The first common voltage lines are disposed adjacent to first sides of the gate electrodes. The second common voltage lines are disposed adjacent to second sides of the gate electrodes.

Abstract: A liquid crystal display includes a pixel electrode including a first subpixel electrode and a second subpixel electrode spaced apart with a gap therebetween, a common electrode facing the pixel electrode, and a liquid crystal layer formed between the pixel electrode and the common electrode and including a plurality of liquid crystal molecules. The first and second subpixel electrodes include a plurality of branches, and each of the first and second subpixel electrodes includes a plurality of subregions. The branches extend in different directions in different subregions.

Abstract: A display panel includes a first sub-pixel electrode and a second sub-pixel electrode alternating with each other to form a horizontal electric field, a first data line transmitting a first data voltage to the first sub-pixel electrode, and a second data line transmitting a second data voltage to the second sub-pixel electrode, wherein the second sub-pixel electrode is formed to overlap the first and second data lines.

Abstract: A liquid crystal display includes: a first substrate and a second substrate disposed opposite the first substrate; a liquid crystal layer interposed between the first and second substrates and including liquid crystal molecules; a gate line which transmits a gate signal; first and second data lines which respectively transmit first and second data voltages, the first and second data voltages having opposite polarities; a first switching element connected to the gate line and the first data line; a second switching element connected to the gate line and the second data line; a first subpixel electrode connected to the first switching element; and a second subpixel electrode connected to the second switching element. The first and second subpixel electrodes overlap portions of the first and second data lines. The first and second subpixel electrodes include first and second branches, respectively, which are alternately arranged between the first and second data lines.

Abstract: A display substrate includes a base substrate, a gate line portion, a data line portion, and a pixel portion. The base substrate includes a display area divided into first to fourth divided display areas, and first to fourth peripheral areas. The gate line portion includes a plurality of first gate lines, and a plurality of second gate lines. The data line portion includes a plurality of first data lines, and a plurality of second data lines. The pixel portion is disposed in the display area to be electrically connected to the first and second gate lines and the first and second data lines, respectively.

Abstract: A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract: An organic light-emitting substrate includes a base substrate, a gate line, a data line, a bias line, an organic light-emitting diode, a switching transistor, a driving transistor and a repair line. The bias line is spaced apart from the gate line and the data line. The organic light-emitting diode includes a pixel electrode, a common electrode and an organic light-emitting part. The switching transistor is connected to the gate line and the data line. The driving transistor is connected to the bias line, the pixel electrode and the switching transistor. The repair line is formed from a pixel metal layer that is identical to the pixel electrode to be spaced apart from the pixel electrode, and is formed along the first direction to be overlapped with the gate line. Therefore, the repair line may repair electric defects of the gate line.

Abstract: A mask includes: a substrate that includes a central area and a peripheral area disposed around the central area; and lenses disposed in rows and columns, in the central area and the peripheral area. The lenses of opposing sides of the peripheral area may be disposed in different rows or columns. For a given amount of input light, the lenses of the peripheral area may focus less light on a substrate than the lenses of the central area. The mask may be disposed over the substrate in different positions, and then the substrate may be irradiated through the mask, while the mask is in each of the positions. The peripheral portion of the mask may be disposed over the same area of the substrate, while the mask is in different ones of the positions.

Abstract: A display panel includes a first sub-pixel electrode and a second sub-pixel electrode alternating with each other to form a horizontal electric field, a first data line transmitting a first data voltage to the first sub-pixel electrode, and a second data line transmitting a second data voltage to the second sub-pixel electrode, wherein the second sub-pixel electrode is formed to overlap the first and second data lines.

Abstract: The present invention relates to a liquid crystal display including a pixel electrode including a first subpixel electrode and a second subpixel electrode spaced apart with a gap therebetween, a common electrode facing the pixel electrode, and a liquid crystal layer formed between the pixel electrode and the common electrode and including a plurality of liquid crystal molecules. The first and second subpixel electrodes include a plurality of branches, and each of the first and second subpixel electrodes includes a plurality of subregions. The branches extend in different directions in different subregions.

Abstract: Provided is a liquid crystal display. The liquid crystal display includes: a substrate; a gate line, a common electrode line and a data line formed on the substrate; an insulating layer formed on the gate line, the common electrode line and the data line; a pixel electrode formed on the insulating layer; a microcavity formed on the pixel electrode and including a liquid crystal injection hole; a common electrode formed on the microcavity; a support member formed on the common electrode; and a capping layer formed on the support member and covering the liquid crystal injection hole, in which the common electrode line and the common electrode are connected to each other through a contact hole formed in a passivation layer.

Abstract: An organic light emitting device including a display panel including a plurality of pixels respectively including a driving transistor and an organic light emitting element; a driving unit to supply a driving signal to the display panel; a signal controller to control the driving unit; a signal modification unit to modify an input image signal based on modification information to generate a modified image signal; and a modification controller to generate and provide the modification information to the signal modification unit. The signal modification unit includes a first modification unit to convert the input image signal into a first modified signal according to first modification information generated based on a characteristic deviation of the driving transistor, and a second modification unit to convert the first modified signal into a second modified signal according to second modification information generated based on a characteristic deviation of the organic light emitting element.

Abstract: A display panel includes a display area including a gate line and a data line, a gate driver integrated on a substrate and connected to one end of the gate line, the gate driver including a plurality of a stage, a signal line connected to the stages; and a blocking member disposed on the signal line and overlapped with the signal line, the blocking member including a plurality of an opening.