Patents by Inventor Chong Han

Chong Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11671300
    Abstract: A discrete Fourier transform spread orthogonal time frequency space modulation method comprises the steps of performing DFT preceding processing and delay-Doppler domain mapping processing on the transmit data symbols, OTFS modulator, and performing delay-Doppler domain demapping processing and IDFT decoding processing on a received signal to realize demodulation; compared with the existing waveforms, including OFDM and DFT-s-OFDM, the proposed DFT-s-OTFS can reduce the bit error rate under high Doppler spread and the peak-to-average power ratio of the transmitted signal at the same time.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: June 6, 2023
    Assignee: SHANGHAI JIAOTONG UNIVERSITY
    Inventors: Chong Han, Yongzhi Wu
  • Publication number: 20230167128
    Abstract: The present invention relates to crystalline polymorph forms of (S)-2-((2-((S)-4-(difluoromethyl)-2-oxooxazolidin-3-yl)-5,6-dihydrobenzo[ƒ]imidazo[1,2-d][1,4]oxazepin-9-yl)amino)propanamide (GDC-0077), having the structure, Formula I: or stereoisomers, geometric isomers, tautomers, and pharmaceutically acceptable salts thereof, and processes of preparing the polymorph forms.
    Type: Application
    Filed: January 26, 2023
    Publication date: June 1, 2023
    Applicant: Genentech, Inc.
    Inventors: Paroma Chakravarty, Chong Han, Sean M. Kelly, Karthik Nagapudi, Scott Savage
  • Patent number: 11626350
    Abstract: A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: April 11, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chong Han Lim, Lee Han Meng@Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen Sueann Lim, Siew Kee Lee
  • Patent number: 11591345
    Abstract: The present invention relates to crystalline polymorph forms of (S)-2-((2-((S)-4-(difluoromethyl)-2-oxooxazolidin-3-yl)-5,6-dihydrobenzo[f]imidazo[1,2-d][1,4]oxazepin-9-yl)amino)propanamide (GDC-0077), having the structure, Formula I: or stereoisomers, geometric isomers, tautomers, and pharmaceutically acceptable salts thereof, and processes of preparing the polymorph forms.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: February 28, 2023
    Assignee: Genentech, Inc.
    Inventors: Paroma Chakravarty, Chong Han, Sean M. Kelly, Karthik Nagapudi, Scott Savage
  • Publication number: 20230016587
    Abstract: A discrete Fourier transform spread orthogonal time frequency space modulation method comprises the steps of performing DFT preceding processing and delay-Doppler domain mapping processing on the transmit data symbols, OTFS modulator, and performing delay-Doppler domain demapping processing and IDFT decoding processing on a received signal to realize demodulation; compared with the existing waveforms, including OFDM and DFT-s-OFDM, the proposed DFT-s-OTFS can reduce the bit error rate under high Doppler spread and the peak-to-average power ratio of the transmitted signal at the same time.
    Type: Application
    Filed: June 16, 2022
    Publication date: January 19, 2023
    Inventors: Chong HAN, Yongzhi WU
  • Publication number: 20220416851
    Abstract: A THz UM-MIMO channel estimation method based on the DCNN comprises the steps: the hybrid spherical and planar-wave modeling (HSPM), by taking a sub-array in the antenna array as a unit, employing the PWM within the sub-array, and employing the SWM among the sub-arrays; estimating the channel parameters between the reference sub-arrays at Tx and Rx through a DCNN, including the angles of departure and arrival, the propagation distance and the path gain; deducing the channel parameters between the reference sub-array and other sub-arrays by utilizing the obtained channel parameters and the geometrical relationships among sub-arrays, and recovering the channel matrix; wherein accurate three-dimensional channel modeling is achieved by the HSPM, which possesses high modeling accuracy and low complexity.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 29, 2022
    Inventors: Chong HAN, Yuhang CHEN, Longfei YAN
  • Publication number: 20220374320
    Abstract: Examples described herein relate to execution of multiple Reliability Availability Serviceability (RAS) processes on different processors of the at least two processors to provide fallback from a first RAS process to a second RAS process executing on a processor of the at least two processors based on failure or timeout of the first RAS process. In some examples, the different processors comprise independently operating processors whereby failure or inoperability of one of the different processors is independent of another of the different processors. In some examples, failure or timeout of the first RAS process comprises failure of the second RAS process to receive an operating status signal from the first RAS process.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 24, 2022
    Inventors: Chuan SONG, Mohan J. KUMAR, Feng JIANG, Yang ZHANG, Chong HAN
  • Publication number: 20220301482
    Abstract: A method for Gamma debugging. The method for Gamma debugging is applicable to a display panel including a first display area and a second display area. A light transmittance of the first display area is greater than that of the second display area. The method includes: selecting, in the second display area, a test area having a same shape and size as the first display area; obtaining a first present brightness value when the test area corresponds to a specified register value under a specified grayscale; determining a plurality of first target brightness values when the first display area corresponds to a plurality of register values under the specified grayscale, according to the first present brightness value and a linear relationship between register values and brightness of the display panel; and performing Gamma debugging on the first display area according to the first target brightness values.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Applicant: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventors: Yuqing WANG, Xinquan CHEN, Xiaobao ZHANG, Chong HAN
  • Publication number: 20220208659
    Abstract: In some examples, a semiconductor package comprises a die pad, a semiconductor die on the die pad, and a mold compound covering the die pad and the semiconductor die. The semiconductor package includes a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2. The mold compound is coupled to the roughened surface. The semiconductor package includes a bond wire coupling the semiconductor die to the roughened surface. The bond wire is directly coupled to the roughened surface without a precious metal positioned therebetween.
    Type: Application
    Filed: January 25, 2021
    Publication date: June 30, 2022
    Inventors: Yee Gin TEA, Chong Han LIM
  • Patent number: 11194522
    Abstract: Apparatuses for computing are disclosed herein. An apparatus may include a set of data reduction modules to perform data reduction operations on sets of (key, value) data pairs to reduce an amount of values associated with a shared key, wherein the (key, value) data pairs are stored in a plurality of queues located in a plurality of solid state drives remote from the apparatus. The apparatus may further include a memory access module, communicably coupled to the set of data reduction modules, to directly transfer individual ones of the sets of queued (key, value) data pairs from the plurality of remote solid state drives through remote random access of the solid state drives, via a network, without using intermediate staging storage. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Xiao Hu, Huan Zhou, Sujoy Sen, Anjaneya R. Chagam Reddy, Mohan J. Kumar, Chong Han
  • Patent number: 11139220
    Abstract: A flexible semiconductor package includes a semiconductor chip accommodated in a cavity formed in a substrate, a molding layer covering an entire upper surface of the substrate and the cavity, and a wiring portion including an insulating layer and a redistribution member provided under lower surfaces of the substrate and the semiconductor chip, wherein the molding layer includes a pre-preg in which a resin is impregnated with a glass fabric, and the molding layer and the insulating layer are attached to the semiconductor chip accommodated in the cavity by a roll-to-roll continuous process.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 5, 2021
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Jea Won Kim, Chong Han Park, Jong Woo Park
  • Publication number: 20210242038
    Abstract: In accordance with at least one example of the disclosure, a system comprises a semiconductor package, comprising a first side surface having a first set of metal contacts extending therefrom; a second side surface having a second set of metal contacts extending therefrom; a top surface; a bottom surface; and an end surface meeting at least one of the first side surface, the second side surface, the top surface, and the bottom surface at a non-rounded edge.
    Type: Application
    Filed: April 22, 2021
    Publication date: August 5, 2021
    Inventors: Anis Fauzi BIN ABDUL AZIZ, Chong Han LIM, Lee Han Meng@Eugene LEE, Wei Fen Sueann LIM
  • Publication number: 20210202356
    Abstract: A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 1, 2021
    Inventors: Chong Han LIM, Lee Han Meng@Eugene LEE, Anis Fauzi BIN ABDUL AZIZ, Wei Fen, Sueann LIM, Siew Kee LEE
  • Patent number: 11028100
    Abstract: The present invention relates to crystalline polymorph forms of (S)-2-((2-((S)-4-(difluoromethyl)-2-oxooxazolidin-3-yl)-5,6-dihydrobenzo[f]imidazo[1,2-d][1,4]oxazepin-9-yl)amino)propanamide (GDC-0077), having the structure, Formula I: or stereoisomers, geometric isomers, tautomers, and pharmaceutically acceptable salts thereof, and processes of preparing the polymorph forms.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: June 8, 2021
    Assignee: Genentech, Inc.
    Inventors: Paroma Chakravarty, Chong Han, Sean M. Kelly, Karthik Nagapudi, Scott Savage
  • Publication number: 20210094970
    Abstract: The present invention relates to crystalline polymorph forms of (S)-2-((2-((S)-4-(difluoromethyl)-2-oxooxazolidin-3-yl)-5,6-dihydrobenzo[f]imidazo[1,2-d][1,4]oxazepin-9-yl)amino)propanamide (GDC-0077), having the structure, Formula I: or stereoisomers, geometric isomers, tautomers, and pharmaceutically acceptable salts thereof, and processes of preparing the polymorph forms.
    Type: Application
    Filed: May 15, 2020
    Publication date: April 1, 2021
    Applicant: Genentech, Inc.
    Inventors: Paroma Chakravarty, Chong Han, Sean M. Kelly, Karthik Nagapudi, Scott Savage
  • Patent number: 10965358
    Abstract: A dynamic signal transmission structure based on a hybrid beamforming technology includes a radio-frequency module and an antenna array connected therewith. The radio-frequency module includes one or more radio-frequency link units connected in parallel, the antenna array includes one or more antenna sub-arrays, and each antenna sub-array is connected with one of the radio-frequency modules. The hybrid beamforming technology includes analog and digital beamforming. In this structure, the analog beamforming parameters and the digital beamforming parameters are constant, and the number of radio-frequency link units in the radio-frequency module, the number of antenna sub-arrays in the antenna array, the analog beamforming parameters, and the digital beamforming parameters are in a quantitative relation.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: March 30, 2021
    Assignees: SHENZHEN INSTITUTE OF TERAHERTZ TECHNOLOGY AND INNOVATION, SHENZHEN INSTITUTE OF TERAHERTZ TECHNOLOGY AND INNOVATION CO., LTD.
    Inventors: Qing Ding, Chong Han, Chen Li, Shitao Yan
  • Publication number: 20210057301
    Abstract: A flexible semiconductor package includes a semiconductor chip accommodated in a cavity formed in a substrate, a molding layer covering an entire upper surface of the substrate and the cavity, and a wiring portion including an insulating layer and a redistribution member provided under lower surfaces of the substrate and the semiconductor chip, wherein the molding layer includes a pre-preg in which a resin is impregnated with a glass fabric, and the molding layer and the insulating layer are attached to the semiconductor chip accommodated in the cavity by a roll-to-roll continuous process.
    Type: Application
    Filed: April 21, 2020
    Publication date: February 25, 2021
    Inventors: Jea Won KIM, Chong Han PARK, Jong Woo PARK
  • Publication number: 20210043466
    Abstract: In accordance with at least one example of the disclosure, a system comprises a semiconductor package, comprising a first side surface having a first set of metal contacts extending therefrom; a second side surface having a second set of metal contacts extending therefrom; a top surface; a bottom surface; and an end surface meeting at least one of the first side surface, the second side surface, the top surface, and the bottom surface at a non-rounded edge.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Inventors: Anis Fauzi BIN ABDUL AZIZ, Chong Han LIM, Lee Han Meng@Eugene LEE, Wei Fen Sueann LIM
  • Publication number: 20200399286
    Abstract: The present invention relates to crystalline polymorph forms of (S)-2-((2-((S)-4-(difluoromethyl)-2-oxooxazolidin-3-yl)-5,6-dihydrobenzo[f]imidazo[1,2-d][1,4]oxazepin-9-yl)amino)propanamide (GDC-0077), having the structure, Formula I: or stereoisomers, geometric isomers, tautomers, and pharmaceutically acceptable salts thereof, and processes of preparing the polymorph forms.
    Type: Application
    Filed: May 15, 2020
    Publication date: December 24, 2020
    Applicant: Genentech, Inc.
    Inventors: Paroma Chakravarty, Chong Han, Sean M. Kelly, Karthik Nagapudi, Scott Savage
  • Patent number: 10870626
    Abstract: The present disclosure relates to processes for preparing (cyclopentyl[d]pyrimidin-4-yl)piperazine compounds, and more particularly relates to processes for preparing (R)-4-(5-methyl-7-oxo-6,7-dihydro-5H-cyclopenta[d] pyrimidin-4-yl)piperazine and N-protected derivatives thereof, which may be used as an intermediate in the synthesis of Ipatasertib (i.e., (S)-2-(4-chlorophenyl)-1-(4-((5R,7R)-7-hydroxy-5-methyl-6,7-dihydro-5H-cyclopenta[d]pyrimidin-4-yl)piperazin-1-yl)-3-(isopropylamino)-propan-1-one). The present disclosure additionally relates to various compounds that are intermediates employed in these processes.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 22, 2020
    Assignees: F. Hoffman-La Roche AG, Genentech, Inc.
    Inventors: Francis Gosselin, Chong Han, Hans Iding, Reinhard Reents, Scott Savage, Beat Wirz