Patents by Inventor Chong Lee
Chong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12176259Abstract: A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.Type: GrantFiled: December 3, 2021Date of Patent: December 24, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yung-Shun Chang, Teck-Chong Lee
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Patent number: 12166009Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.Type: GrantFiled: August 29, 2023Date of Patent: December 10, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
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Patent number: 12164083Abstract: An optical imaging system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens sequentially disposed from an object side. The optical imaging system satisfies |Pnu|[10?6° C.?1 mm?1]?30, where Pnu is ?Pnui in which i=1, 2, . . . , 7, Pnui is 1/(vti·fi), vti is [DTni/(ni?1)?CTEi]?1, fi is an effective focal length of an i-th lens, ni is a refractive index of the i-th lens, DTni is a rate (dni/dT) of change of the refractive index according to a temperature of the i-th lens, and CTEi is a thermal expansion coefficient of the i-th lens.Type: GrantFiled: July 19, 2021Date of Patent: December 10, 2024Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Kyu Min Chae, Eun Chong Lee
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Publication number: 20240178158Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.Type: ApplicationFiled: February 6, 2024Publication date: May 30, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Po-Hsien KE, Teck-Chong LEE, Chih-Pin HUNG
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Publication number: 20240170396Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Shun CHANG, Sheng-Wen YANG, Teck-Chong LEE, Yen-Liang HUANG
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Publication number: 20240142744Abstract: A lens module is provided. The lens module includes a first lens, a second lens, and a third lens sequentially disposed from an object side to an imaging side, a first spacing member disposed between the first lens and the second lens and having a first passage extending in a direction that intersects an optical axis, a second spacing member disposed between the second lens and the third lens and having a second passage extending in a direction that intersects the optical axis, and a lens barrel configured to accommodate the first lens, the second lens, the third lens, the first spacing member and the second spacing member, and configured to have a first connection passage disposed on an inner side surface and connected to the first passage and the second passage.Type: ApplicationFiled: September 6, 2023Publication date: May 2, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Eun Chong LEE, Hwan Soo PARK, Kyu Min CHAE, Hyuk Joo KIM
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Patent number: 11894317Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.Type: GrantFiled: August 26, 2020Date of Patent: February 6, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Po-Hsien Ke, Teck-Chong Lee, Chih-Pin Hung
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Patent number: 11887928Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.Type: GrantFiled: December 17, 2021Date of Patent: January 30, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yung-Shun Chang, Sheng-Wen Yang, Teck-Chong Lee, Yen-Liang Huang
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Patent number: 11855034Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.Type: GrantFiled: May 28, 2021Date of Patent: December 26, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chung-Hung Lai, Chin-Li Kao, Chih-Yi Huang, Teck-Chong Lee
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Publication number: 20230411349Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.Type: ApplicationFiled: August 29, 2023Publication date: December 21, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
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Publication number: 20230338117Abstract: A method of managing teeth performed in a processor-based device includes: displaying a first oral measurement image including tooth measurement images in a tooth shape to measure state information of each of user’s teeth; receiving state information of a target teeth of the user measured from a tooth diagnostic device; receiving a selection signal input for selecting a first tooth measurement image from among the tooth measurement images; matching state information of the target tooth with state information of the first tooth measurement image; and representing the state information of the first tooth measurement image in the first oral measurement image.Type: ApplicationFiled: November 21, 2022Publication date: October 26, 2023Inventors: Ho Jung SON, Myung Seon RYOU, Yoon A KIM, Chong LEE, Won Hyung RYOU
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Patent number: 11764311Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.Type: GrantFiled: September 28, 2021Date of Patent: September 19, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Pin Tsai, Tsung-Yueh Tsai, Teck-Chong Lee
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Patent number: 11737504Abstract: A front cover for a helmet connectable to a shell for the helmet for covering an upper side, a rear side, and two sides of the head of a wearer so as to protect the upper side, the rear side, and two sides of the head of the wearer, is provided. The front cover includes a jaw protection portion configured to protect the wearer's jaw when the front cover is connected to the shell, and a jaw mediation portion connected to the jaw protection portion and configured to serve to mediate the jaw protection portion and the shell by being connected to the shell. When the jaw protection portion is connected to the shell by the jaw mediation portion, the jaw protection portion is rotatable based on the shell.Type: GrantFiled: November 4, 2020Date of Patent: August 29, 2023Assignee: KIDO SPORTS CO., LTD.Inventors: Young Chong Lee, Geun Ho Jwa
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Patent number: 11742324Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.Type: GrantFiled: May 17, 2021Date of Patent: August 29, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
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Publication number: 20230261036Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.Type: ApplicationFiled: April 25, 2023Publication date: August 17, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Hua CHEN, Teck-Chong LEE
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Publication number: 20230228977Abstract: An optical imaging system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens sequentially disposed in numerical order along an optical axis of the optical imaging system from an object side of the optical imaging system toward an imaging plane of the optical imaging system, wherein the first to seventh lenses are spaced apart from each other along the optical axis, and the optical imaging system satisfies 0.4 < L1TR/L7TR < 1.9, where L1TR is an overall outer diameter of the first lens, L7TR is an overall outer diameter of the seventh lens, and L1TR and L7TR are expressed in a same unit of measurement.Type: ApplicationFiled: March 29, 2023Publication date: July 20, 2023Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Hag Chul KIM, Eun Chong LEE, Yong Joo JO, Ga Young AN
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Publication number: 20230197600Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Shun CHANG, Sheng-Wen YANG, Teck-Chong LEE, Yen-Liang HUANG
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Publication number: 20230178444Abstract: A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.Type: ApplicationFiled: December 3, 2021Publication date: June 8, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Shun CHANG, Teck-Chong LEE
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Patent number: 11637172Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.Type: GrantFiled: October 28, 2020Date of Patent: April 25, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Hua Chen, Teck-Chong Lee
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Patent number: 11621220Abstract: An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.Type: GrantFiled: March 25, 2021Date of Patent: April 4, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yung-Shun Chang, Chih-Pin Hung, Teck-Chong Lee, Chih-Yi Huang