Patents by Inventor Chong Lee

Chong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11545427
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Chien-Hua Chen, Teck-Chong Lee, Hung-Yi Lin, Pao-Nan Lee, Hsin Hsiang Wang, Min-Tzu Hsu, Po-Hao Chen
  • Publication number: 20220413264
    Abstract: An optical imaging system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens sequentially disposed in numerical order along an optical axis of the optical imaging system from an object side of the optical imaging system toward an imaging plane of the optical imaging system, wherein the first to seventh lenses are spaced apart from each other along the optical axis, and the optical imaging system satisfies 0.4<L1TR/L7TR<1.9, where L1TR is an overall outer diameter of the first lens, L7TR is an overall outer diameter of the seventh lens, and L1TR and L7TR are expressed in a same unit of measurement.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 29, 2022
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hag Chul KIM, Eun Chong LEE, Yong Joo JO, Ga Young AN
  • Publication number: 20220408870
    Abstract: A front cover for a helmet connectable to a shell for the helmet for covering an upper side, a rear side, and two sides of the head of a wearer so as to protect the upper side, the rear side, and two sides of the head of the wearer, is provided. The front cover includes a jaw protection portion configured to protect the wearer's jaw when the front cover is connected to the shell, and a jaw mediation portion connected to the jaw protection portion and configured to serve to mediate the jaw protection portion and the shell by being connected to the shell. When the jaw protection portion is connected to the shell by the jaw mediation portion, the jaw protection portion is rotatable based on the shell.
    Type: Application
    Filed: November 4, 2020
    Publication date: December 29, 2022
    Inventors: Young Chong LEE, Geun Ho JWA
  • Publication number: 20220384381
    Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung-Hung LAI, Chin-Li KAO, Chih-Yi HUANG, Teck-Chong LEE
  • Patent number: 11515241
    Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 29, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Patent number: 11508655
    Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Meng-Wei Hsieh, Teck-Chong Lee
  • Patent number: 11495572
    Abstract: A semiconductor package device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulation layer. The transparent carrier has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer. The first insulation layer is disposed on the transparent carrier and covers the first patterned conductive layer.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Publication number: 20220317420
    Abstract: An optical imaging system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens sequentially disposed from an object side. The optical imaging system satisfies |Pnu| [10?6° C.?1 mm?1]?30, where Pnu is ?Pnui in which i=1, 2, . . . , 7, Pnui is 1/(vti·fi), vti is [DTni/(ni?1)?CTEi]?1, fi is an effective focal length of an i-th lens, ni is a refractive index of the i-th lens, DTni is a rate (dni/dT) of change of the refractive index according to a temperature of the i-th lens, and CTEi is a thermal expansion coefficient of the i-th lens.
    Type: Application
    Filed: July 19, 2021
    Publication date: October 6, 2022
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyu Min CHAE, Eun Chong LEE
  • Publication number: 20220310500
    Abstract: An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Shun CHANG, Chih-Pin HUNG, Teck-Chong LEE, Chih-Yi HUANG
  • Publication number: 20220269033
    Abstract: An optical imaging system including a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens disposed in order from an object side, wherein one or more of the first to sixth lenses is disposed between a stop and an imaging plane and of those, one or more has positive refractive power and one is made of a glass material, and four or more of the first to sixth lenses are made of a plastic material.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 25, 2022
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyu Min CHAE, Eun Chong LEE
  • Patent number: 11373967
    Abstract: A semiconductor device package includes a first semiconductor device; a second semiconductor device; and a first redistribution layer disposed on the first semiconductor device and having a side wall defining an opening that exposes the first semiconductor device. The side wall of the first redistribution layer has an average surface roughness (Ra) in a range up to 2 micrometers (?m).
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 28, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee, Sheng-Wen Yang
  • Patent number: 11360285
    Abstract: An optical imaging system including a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens disposed in order from an object side, wherein one or more of the first to sixth lenses is disposed between a stop and an imaging plane and of those, one or more has positive refractive power and one is made of a glass material, and four or more of the first to sixth lenses are made of a plastic material.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: June 14, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyu Min Chae, Eun Chong Lee
  • Patent number: 11276620
    Abstract: A package structure includes a wiring structure, at least one electronic device, a reinforcement structure, a plurality of conductive vias and an encapsulant. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The electronic device is electrically connected to the wiring structure. The reinforcement structure is disposed on a surface of the wiring structure, and includes a thermoset material. The conductive vias is disposed in the reinforcement structure. The encapsulant covers the electronic device.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Publication number: 20220068839
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Hsien KE, Teck-Chong LEE, Chih-Pin HUNG
  • Patent number: 11258978
    Abstract: The present invention encompasses methods and systems of representing video in continuous time. Photons incident on pixels in an imaging array are continuously captured using a continuous time imaging sensor array to produce respective continuous time analog signals without any discontinuity in time. At each pixel, the respective continuous time analog signal is modulated into respective continuous time binary analog signals. The continuous time binary analog signals from all pixels can then be aggregated to produce a frame free video. Further, at each pixel, the respective continuous time analog signal may be modulated using a continuous time sigma delta modulator to produce the corresponding continuous time binary analog signal. The sigma delta modulator may be one of charge-based or current-based.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: February 22, 2022
    Assignee: Solsona Enterprise, LLC
    Inventor: Chong Lee
  • Publication number: 20220020885
    Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 20, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Tsung-Yueh TSAI, Teck-Chong LEE
  • Publication number: 20210409742
    Abstract: The present invention encompasses methods and systems of transcoding frame-based video to frame free video is provided. The method comprises receiving a frame-based video stream, upconverting the received frame-based video stream to produce an upconverted frame-based video stream at a higher frame rate than the received frame-based video stream, and modulating the upconverted frame-based video stream using discrete time sigma delta modulation to produce a frame free video stream. In addition, complimentary methods and systems are disclosed for transcoding frame free video to frame-based video.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventor: Chong Lee
  • Patent number: 11181719
    Abstract: An optical imaging system includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens sequentially disposed in numerical order along an optical axis of the optical imaging system from an object side of the optical imaging system toward an imaging plane of the optical imaging system, wherein the first to seventh lenses are spaced apart from each other along the optical axis, and the optical imaging system satisfies 0.4<L1TR/L7TR<1.9, where L1TR is an overall outer diameter of the first lens, L7TR is an overall outer diameter of the seventh lens, and L1TR and L7TR are expressed in a same unit of measurement.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 23, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hag Chul Kim, Eun Chong Lee, Yong Joo Jo, Ga Young An
  • Publication number: 20210344859
    Abstract: The present invention encompasses methods and systems of representing video in continuous time. Photons incident on pixels in an imaging array are continuously captured using a continuous time imaging sensor array to produce respective continuous time analog signals without any discontinuity in time. At each pixel, the respective continuous time analog signal is modulated into respective continuous time binary analog signals. The continuous time binary analog signals from all pixels are aggregated to produce a frame free video. Each pixel may comprise a continuous time sigma delta modulator and a photodiode having a capacitance. At each pixel, the respective continuous time analog signal is modulated using the continuous time sigma delta modulator to produce the corresponding continuous time binary analog signal. The capacitance of the photodiode functions as a charge integrator.
    Type: Application
    Filed: July 2, 2021
    Publication date: November 4, 2021
    Inventor: Chong Lee
  • Patent number: 11133423
    Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Pin Tsai, Tsung-Yueh Tsai, Teck-Chong Lee