Patents by Inventor Chong Lee

Chong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9990488
    Abstract: A method and associated computing device. A first arrangement of numeric characters 0-9 is displayed, on a touch screen of the computing device, for an entry of a confidential sequence of numeric characters by a user during display of the first arrangement of the numeric characters 0-9 in ten respective regions of the touch screen. Each region includes (i) a unique numeric character and (ii) a graphical design that does not include the unique numeric character. The graphical design in each region is a different graphical design in each region. Each region has a closed exterior boundary and is totally filled with the graphical design consisting of a background pattern or no pattern. A graphical characteristic is instantiated differently for each numeric character displayed in the first arrangement. User touches are received on the displayed first arrangement of the confidential sequence of numeric characters to authenticate or authorize the user.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 5, 2018
    Assignee: Softlayer Technologies, Inc.
    Inventor: Chong Lee
  • Publication number: 20180138262
    Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 17, 2018
    Inventors: Chien-Hua CHEN, Teck-Chong LEE
  • Publication number: 20180138113
    Abstract: A semiconductor device package includes a semiconductor chip, a glass substrate having a first surface facing the semiconductor chip and a second surface opposite to the first surface, the glass substrate defining a hole that traverses the glass substrate from the first surface to the second surface, an interconnect structure disposed in the hole, and a conductive bump disposed adjacent to the interconnect structure and protruded from the second surface, wherein the conductive bump and the interconnect structure include a same material.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 17, 2018
    Inventors: Chien-Hua CHEN, Teck-Chong LEE, Yung-Shun CHANG
  • Publication number: 20180103710
    Abstract: A helmet according to the present invention includes: a head frame being open toward the user's face, designed to cover the user's head, and having a rotation part at both sides; a face frame coupled to be turned up and down about the rotation parts and selectively closing the opening of the head frame; and a sun visor disposed at an upper portion of the face frame and coupled to be turned up and down about the rotation parts, in which the sun visor is turned up with the face frame when the face frame is turned up to open the opening of the head frame, and is fixed regardless of rotation of the face frame when a predetermined rotational limit is reached.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 19, 2018
    Inventors: Young Il KIM, Young Chong LEE
  • Patent number: 9947561
    Abstract: A semiconductor encapsulation apparatus for encapsulating a semiconductor device on a substrate, the apparatus comprising a mold comprising a cavity pressure zone that is configured to be at a molding process pressure during molding, a base vacuum pump conduit connecting a base vacuum pump to the cavity pressure zone, a base vacuum valve located along the base vacuum pump conduit such that the base vacuum pump is in fluid communication with the cavity pressure zone when the base vacuum valve is open, a reservoir vacuum pump conduit connecting a reservoir vacuum pump to the base vacuum pump conduit, and a reservoir vacuum valve located along the reservoir vacuum pump conduit such that the reservoir vacuum pump is in fluid communication with the base vacuum pump conduit when the reservoir vacuum valve is open.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: April 17, 2018
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Teng Hock Kuah, Chee Toh Teh, Shu Chuen Ho, Kai Wu, Chin Chong Lee
  • Publication number: 20180096125
    Abstract: A method and associated computing device. A first arrangement of numeric characters 0-9 is displayed, on a touch screen of the computing device, for an entry of a confidential sequence of numeric characters by a user during display of the first arrangement of the numeric characters 0-9 in ten respective regions of the touch screen. Each region includes (i) a unique numeric character and (ii) a graphical design that does not include the unique numeric character. The graphical design in each region is a different graphical design in each region. Each region has a closed exterior boundary and is totally filled with the graphical design consisting of a background pattern or no pattern. A graphical characteristic is instantiated differently for each numeric character displayed in the first arrangement. User touches are received on the displayed first arrangement of the confidential sequence of numeric characters to authenticate or authorize the user.
    Type: Application
    Filed: November 21, 2017
    Publication date: April 5, 2018
    Inventor: Chong Lee
  • Patent number: 9929132
    Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: March 27, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Teck-Chong Lee, Chien-Hua Chen, Yung-Shun Chang, Pao-Nan Lee
  • Patent number: 9898597
    Abstract: A method and associated computing device, A first arrangement of numeric characters 0-9 is displayed, on a touch screen of the computing device, for an entry of a confidential sequence of numeric characters by a user during display of the first arrangement of the numeric characters 0-9 in ten respective regions of the touch screen. Each region includes (i) a unique numeric character and (ii) a graphical design that does not include the unique numeric character. The graphical design in each region is a different graphical design in each region. Each region has a closed exterior boundary and is totally filled with the graphical design consisting of a background pattern or no pattern. A graphical characteristic is instantiated differently for each numeric character displayed in the first arrangement. User touches are received on the displayed first arrangement of the confidential sequence of numeric characters to authenticate or authorize the user.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: February 20, 2018
    Assignee: Softlayer Technologies, Inc.
    Inventor: Chong Lee
  • Patent number: 9881917
    Abstract: A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: January 30, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Chiang Shih, Sheng-Chi Hsieh, Chien-Hua Chen, Teck-Chong Lee
  • Patent number: 9857593
    Abstract: Natural-scene light is polarized so the light exiting the polarizer and entering a glass assembly has a first polarization. Light having a second polarization substantially orthogonal to the first polarization is launched into the glass assembly and directed normal to the glass assembly and into a zone plate assembly, along with the natural-scene light. A first plurality of electric fields is established in the zone assembly to form at least one zone plate that modulates the launched light without modulating the natural-scene light. The first plurality of electric fields is disestablished and a second plurality of electric fields is established in the zone plate assembly to reposition the at least one zone plate in the liquid crystal plate. Disestablishment and establishment of electric fields is repeated at a sufficient rate so that an image defined by a number of pixel spots formed on a retina is perceived by a viewer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: John Hong, Jian Ma, Chong Lee, Tallis Chang, Jay Yun, Robert Sean Daley, Frederick Kim
  • Patent number: 9837352
    Abstract: A semiconductor device includes a substrate, at least one integrated passive device, a first redistribution layer, a second redistribution layer, and conductive vias. The at least one integrated passive device includes at least one capacitor disposed adjacent to a first surface of the substrate. The first redistribution layer is disposed adjacent to the first surface of the substrate. The second redistribution layer is disposed adjacent to a second surface of the substrate. The conductive vias extend through the substrate, and electrically connect the first redistribution layer and the second redistribution layer.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: December 5, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Chien-Hua Chen, Teck-Chong Lee
  • Publication number: 20170252954
    Abstract: A semiconductor encapsulation apparatus for encapsulating a semiconductor device on a substrate, the apparatus comprising a mold comprising a cavity pressure zone that is configured to be at a molding process pressure during molding, a base vacuum pump conduit connecting a base vacuum pump to the cavity pressure zone, a base vacuum valve located along the base vacuum pump conduit such that the base vacuum pump is in fluid communication with the cavity pressure zone when the base vacuum valve is open, a reservoir vacuum pump conduit connecting a reservoir vacuum pump to the base vacuum pump conduit, and a reservoir vacuum valve located along the reservoir vacuum pump conduit such that the reservoir vacuum pump is in fluid communication with the base vacuum pump conduit when the reservoir vacuum valve is open.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 7, 2017
    Inventors: Teng Hock KUAH, Chee Toh TEH, Shu Chuen HO, Kai WU, Chin Chong LEE
  • Publication number: 20170155529
    Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 1, 2017
    Inventors: Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee
  • Publication number: 20170133360
    Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.
    Type: Application
    Filed: January 13, 2017
    Publication date: May 11, 2017
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Teck-Chong LEE, Chien-Hua CHEN, Yung-Shun CHANG, Pao-Nan LEE
  • Publication number: 20170116406
    Abstract: A method and associated computing device, A first arrangement of numeric characters 0-9 is displayed, on a touch screen of the computing device, for an entry of a confidential sequence of numeric characters by a user during display of the first arrangement of the numeric characters 0-9 in ten respective regions of the touch screen. Each region includes (i) a unique numeric character and (ii) a graphical design that does not include the unique numeric character. The graphical design in each region is a different graphical design in each region. Each region has a closed exterior boundary and is totally filled with the graphical design consisting of a background pattern or no pattern. A graphical characteristic is instantiated differently for each numeric character displayed in the first arrangement. User touches are received on the displayed first arrangement of the confidential sequence of numeric characters to authenticate or authorize the user.
    Type: Application
    Filed: January 3, 2017
    Publication date: April 27, 2017
    Inventor: Chong Lee
  • Publication number: 20170103946
    Abstract: A semiconductor device includes a substrate, at least one integrated passive device, a first redistribution layer, a second redistribution layer, and conductive vias. The at least one integrated passive device includes at least one capacitor disposed adjacent to a first surface of the substrate. The first redistribution layer is disposed adjacent to the first surface of the substrate. The second redistribution layer is disposed adjacent to a second surface of the substrate. The conductive vias extend through the substrate, and electrically connect the first redistribution layer and the second redistribution layer.
    Type: Application
    Filed: June 10, 2016
    Publication date: April 13, 2017
    Inventors: Yung-Shun Chang, Chien-Hua Chen, Teck-Chong Lee
  • Patent number: 9577027
    Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 21, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Teck-Chong Lee, Chien-Hua Chen, Yung-Shun Chang, Pao-Nan Lee
  • Publication number: 20170047276
    Abstract: The present disclosure relates to a semiconductor device package and a method for manufacturing the same. The semiconductor device package comprises a substrate, a first patterned conductive layer, an insulator layer, a second patterned conductive layer, and a dielectric layer. The first patterned conductive layer is disposed on a surface of the substrate. The insulator layer is disposed on the surface of the substrate and covers the first patterned conductive layer. The second patterned conductive layer is fully encapsulated by the insulator layer. The dielectric layer is disposed on the insulator layer.
    Type: Application
    Filed: August 13, 2015
    Publication date: February 16, 2017
    Inventors: Chien-Hua CHEN, Teck-Chong LEE, Chi-Han CHEN, Sheng-Chi HSIEH
  • Publication number: 20170018550
    Abstract: A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.
    Type: Application
    Filed: July 16, 2015
    Publication date: January 19, 2017
    Inventors: Hsu-Chiang SHIH, Sheng-Chi HSIEH, Chien-Hua CHEN, Teck-Chong LEE
  • Publication number: 20160018657
    Abstract: Natural-scene light is polarized so the light exiting the polarizer and entering a glass assembly has a first polarization. Light having a second polarization substantially orthogonal to the first polarization is launched into the glass assembly and directed normal to the glass assembly and into a zone plate assembly, along with the natural-scene light. A first plurality of electric fields is established in the zone assembly to form at least one zone plate that modulates the launched light without modulating the natural-scene light. The first plurality of electric fields is disestablished and a second plurality of electric fields is established in the zone plate assembly to reposition the at least one zone plate in the liquid crystal plate. Disestablishment and establishment of electric fields is repeated at a sufficient rate so that an image defined by a number of pixel spots formed on a retina is perceived by a viewer.
    Type: Application
    Filed: September 25, 2015
    Publication date: January 21, 2016
    Inventors: John Hong, Jian Ma, Chong Lee, Tallis Chang, Jay Yun, Robert Sean Daley, Frederick Kim