Abstract: A system, devices and procedures for providing QoS monitoring in a 5G network are described. The QoS monitoring is per QoS flow per UE or GTP-U path QoS monitoring. A SMF sends a request to a UPF and NG-RAN to report UL/DL packet delay and RTT between the UPF and a UE or an N3 and N9 interface, along with thresholds for reporting the measurements. The UPF sends a report containing the measurements when the threshold is met. The delays include average, minimum and maximum packet delays. The request also indicates a state of QoS monitoring, S-NSSAI and 5QI to monitor, whether event-based/periodic/session release-based QoS monitoring reporting per QoS flow per UE is supported, minimum waiting time between consecutive reports for event-triggered QoS monitoring reporting, and a period to report the measured packet delay.

Abstract: A camera module includes an imaging lens assembly, an image sensor, a first reflecting member and a first driving apparatus. The imaging lens assembly is for converging an imaging light on an image surface. The image sensor is disposed on the image surface. The first reflecting member is located on an image side of the imaging lens assembly, the first reflecting member is for folding the imaging light, and has a first translational degrees of freedom. The first reflecting member is assembled on the first driving apparatus, and the first driving apparatus is for driving the first reflecting member moving along the first translational degrees of freedom.

Abstract: An apparatus for self-optimization of a Network Slice Instance, NSI, comprising network slice related management functions is provided. The apparatus can include a Network Slice Management Function, NSMF, operable to monitor a performance of a Network Slice Instance in use, and evaluate whether the Network Slice Instance meets a received set of Network Slice requirements, wherein the received set of Network Slice requirements are received from a Service Management Function, SMF, and/or an Operator's target for performance of the Network Slice Instance. The apparatus can also include a Network Slice Subnet Management Function, in communication with the Network Slice Management Function, and operable to modify a Network Slice SubNet Instance, NSSI, for use in the Network Slice Instance in use in order to meet the received Network Slice requirements.

Abstract: The disclosure provides a digital-to-analog conversion device and an operation method thereof. The digital-to-analog conversion device includes a digital-to-analog conversion circuit and a slew rate enhancement circuit. The digital-to-analog conversion circuit is configured to convert a digital code into an analog voltage. An output terminal of the digital-to-analog conversion circuit outputs the analog voltage to a load circuit. A control terminal of the slew rate enhancement circuit is coupled to the digital-to-analog conversion circuit to receive a control voltage following the analog voltage. The slew rate enhancement circuit is coupled to the output terminal of the digital-to-analog conversion circuit. The slew rate enhancement circuit enhances the slew rate at the output terminal of the digital-to-analog conversion circuit based on the control voltage.

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Abstract: A cell region of a semiconductor device, the cell region including: components (representing a first circuit) including alpha info conductors and dummy conductors which are substantially collinear correspondingly with reference tracks, regarding the first circuit, the alpha info conductors beipng correspondingly for one or more input and/or output signals, or one or more internal signals, and for a majority of the reference tracks, first ends correspondingly of the alpha info conductors or the dummy conductors being aligned and proximal to a first side of the cell region; a first alpha info conductor being on a first reference track and being an intra-cell conductor which does not extend beyond the first side nor a second side of the cell region; and a portion of a first beta info conductor of a second circuit (represented by components of an external cell region) being on the first reference track.

Abstract: The present disclosure provides for use of variants of C-type natriuretic peptide (CNP), and novel pharmaceutical compositions and formulations comprising CNP variant peptides for the treatment of skeletal dysplasias, one or more symptoms of skeletal dysplasias, such as long bone growth or growth velocity, and other disorders having a skeletal dysplasia and/or CNP-associated symptom or component.

Abstract: Methods and systems are provided for predicting temporal Lidar labels with a single click. In some aspects, a process can include steps for receiving point cloud data based on a detected object from an autonomous vehicle, determining an object based on the point cloud data of the detected object and corresponding models related to the detected object, updating the models based on the point cloud data of the detected object and selected object labels, the selected object labels being based on 3D bounding boxes of the detected object, and providing the updated models to the autonomous vehicle for deployment. Systems and machine-readable media are also provided.

Abstract: Described herein are methods, systems, and computer-readable media for the generation of classifications of content. Techniques may extract and clean information associated with a first instance of content associated with a first person. Techniques may next classify the cleaned information into a first set of categories and determine a second set of categories based on the cleaned information associated with the first and other instances of content and aggregate the cleaned information using the second set of categories into groups. Techniques further determine a third set of categories of information associated with a group of people including the first person to generate metadata for the information associated with the group of people. Techniques to generate metadata include using frequency data associated with the information based on the first set of categories, the second set of categories, and the third set of categories.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device including a shallow trench isolation (STI) structure disposed between a first side and a second side of the semiconductor substrate. An intermetal dielectric structure comprising a first metal interconnect is on the second side. A first etching process is performed to form a first trench extending from the first side of the semiconductor substrate to the STI structure. An etch stop layer is deposited on the first side. A dielectric material is deposited into the first trench to form a dielectric spacer. A second trench is etched during a second etching process. The second trench is aligned with the first trench and extends through the STI structure to the first metal interconnect. A conductive material is deposited into the second trench to form a contact pad that contacts the first metal interconnect.

Abstract: In one aspect, the disclosure relates to methods and compositions for treatment of cancer cachexia. In a further aspect, the composition is a pharmaceutical composition comprising a class I/IIB HDAC inhibitor and an androgen. In a still further aspect, the method of treatment comprises administering a class I/IIB HDAC inhibitor and an androgen to a subject or patient who has been diagnosed as having cancer cachexia. In some aspects, the class I/IIB HDAC inhibitor is a compound known as AR-42.

Abstract: A semiconductor structure includes a substrate and a gate-all-around field effect transistor disposed over the substrate. The gate-all-around field effect transistor includes a first source-drain region; a second source-drain region; at least one channel region interconnecting the first and second source drain regions; and a gate structure surrounding the at least one channel region. A self-aligned substrate isolation (SASI) layer is located between the substrate and the gate structure and extends over a width of the gate structure.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes an electronic component and a first connection element. The electronic component includes a conductive wire and a magnetic layer encapsulating the conductive wire. The first connection element is electrically connected to the conductive wire. The first connection element is disposed outside the magnetic layer.

Abstract: An optical imaging module includes an imaging lens assembly, an optical path folding element, and a light-blocking element. The imaging lens assembly includes at least one optical lens element. The optical path folding element is disposed at an image side of the imaging lens assembly, and the optical path folding element has a light incident surface, a light exiting surface, and at least one optical reflective surface. The light-blocking element is disposed opposite to the at least one optical reflective surface, and the light-blocking element includes an interval area that maintains a distance from the optical path folding element. The at least one optical reflective surface is an optical total reflection surface configured to totally internally reflect imaging light of the optical imaging module in the optical path folding element. The interval area of the light-blocking element and the optical total reflection surface form an air slit therebetween.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a mask layer on a first side of a semiconductor substrate. The mask layer comprises a plurality of sidewalls defining a plurality of openings. A first etch process is performed on the semiconductor substrate to form a plurality of recesses within the semiconductor substrate. A second etch process is performed on the semiconductor substrate to expand the plurality of recesses and form a plurality of protrusions that comprise curved opposing sidewalls.

Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

Abstract: Methods and systems include neural network-based image processing and blending circuitry to blend an output of the neural network to compensate for potential artifacts from the neural network-based image processing. The neural network(s) apply image processing to image data using one or more neural networks as processed data. Enhance circuitry enhances the image data in a scaling circuitry to generate enhanced data. Blending circuitry receives the processed image data and the enhanced data along with an image plane of the processed data. The blending circuitry also determines whether the image processing using the one or more neural networks has applied a change to the image data greater than a threshold amount. The blending circuitry then, based at least in part in response to the change being greater than the threshold amount and/or edge information of the image data, blends the processed data with the enhanced data.

Abstract: A transmission system is disclosed including a driver circuit. The driver circuit includes multiplexer circuits that receive parallel data and operate as a differential pair. At least one of the multiplexer circuits is coupled to a first circuit node and a second circuit node of the driver circuit. The at least one the multiplexer circuits outputs serial data from the multiplexer circuits at the first and second circuit nodes. The first and second nodes are coupled to a differential output network. The first and second nodes are coupled to an inductor circuit. The first and second nodes are coupled to a cross-coupled circuit. The inductor circuit drains driver circuit current at the first circuit node. The second circuit node and the cross-coupled circuit steer driver circuit current at the first circuit node and the second circuit node.

Abstract: Some embodiments are related to a fifth generation (5G) or sixth generation (6G) wireless communications system and network components to generate performance measurements for subscriber data and parameter provisioning in a unified data management system. Some embodiments are related to a wireless communications system and network components to generate data volume performance measurement for network functions supporting edge computing. Other embodiments are described and claimed.

Abstract: A control method is applied to a first device. The first device includes a first processor and a second processor. The method includes responding to a boot command for the first device to boot the first processor and responding to control by the first processor to boot the second processor to execute a plurality of boot tasks corresponding to the first device in parallel. The second processor is configured to execute at least one boot task of the plurality of boot tasks.