Patents by Inventor Christian Geissler

Christian Geissler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200176436
    Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 4, 2020
    Inventors: Sven ALBERS, Klaus REINGRUBER, Richard PATTEN, Georg SEIDEMANN, Christian GEISSLER
  • Patent number: 10672731
    Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: June 2, 2020
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Klaus Reingruber, Georg Seidemann, Christian Geissler, Richard Patten
  • Publication number: 20200156933
    Abstract: A production method includes providing a semiconductor substrate with a wiring layer stack having cutouts on a first main surface region of the semiconductor substrate at which MEMS components are arranged in an exposed manner in the cutouts and projecting through contact elements are arranged at metallization regions of the wiring layer stack; applying a b-stage material layer cured in an intermediate stage on the wiring layer stack, such that the cutouts are covered by the b-stage material layer and the vertically projecting through contact elements are introduced into the b-stage material layer; curing the b-stage material layer to obtain a cured b-stage material layer; thinning the cured b-stage material layer; and applying a redistribution layer (RDL) structure on the thinned, cured b-stage material layer to obtain an electrical connection between the wiring layer stack and the RDL structure via the through contact elements.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Inventors: Matthias Steiert, Christian Geissler, Karolina Zogal
  • Patent number: 10651102
    Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 12, 2020
    Assignee: Intel IP Corporation
    Inventors: Klaus Reingruber, Christian Geissler, Georg Seidemann, Sonja Koller
  • Patent number: 10584028
    Abstract: A production method includes providing a semiconductor substrate with a wiring layer stack having cutouts on a first main surface region of the semiconductor substrate at which MEMS components are arranged in an exposed manner in the cutouts and projecting through contact elements are arranged at metallization regions of the wiring layer stack; applying a b-stage material layer cured in an intermediate stage on the wiring layer stack, such that the cutouts are covered by the b-stage material layer and the vertically projecting through contact elements are introduced into the b-stage material layer; curing the b-stage material layer to obtain a cured b-stage material layer; thinning the cured b-stage material layer; and applying a redistribution layer (RDL) structure on the thinned, cured b-stage material layer to obtain an electrical connection between the wiring layer stack and the RDL structure via the through contact elements.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 10, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Matthias Steiert, Christian Geissler, Karolina Zogal
  • Patent number: 10549985
    Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dominic Maier, Matthias Steiert, Chau Fatt Chiang, Christian Geissler, Bernd Goller, Thomas Kilger, Johannes Lodermeyer, Franz-Xaver Muehlbauer, Chee Yang Ng, Beng Keh See, Claus Waechter
  • Publication number: 20200006174
    Abstract: A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.
    Type: Application
    Filed: June 20, 2019
    Publication date: January 2, 2020
    Inventors: Christian GEISSLER, Walter Hartner, Claus Waechter, Maciej Wojnowski
  • Patent number: 10522454
    Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Andreas Wolter, Georg Seidemann, Sven Albers, Christian Geissler
  • Patent number: 10522485
    Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 31, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Patent number: 10490527
    Abstract: A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 26, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Patent number: 10446541
    Abstract: An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 15, 2019
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Christian Geissler, Klaus Reingruber
  • Patent number: 10442457
    Abstract: A steering column may comprise a casing tube and a steering spindle that is mounted in the casing tube so as to be rotatable about a longitudinal axis. The steering column may further comprise fastening elements for fastening the steering column on the vehicle body. The steering column may include a pivot bearing for height adjustment of the steering column. The pivot bearing may be provided on a region of the steering column that is remote from the steering wheel. Further, the pivot bearing may be disposed or formed in a supporting element that is fastened non-releasably on the casing tube.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 15, 2019
    Assignees: THYSSENKRUPP PRESTA AG, THYSSENKRUPP AG
    Inventors: Eric Gstöhl, Sven Hausknecht, Stefan-Hermann Loos, Frank Pasch, Christian Geissler
  • Patent number: 10427706
    Abstract: A steering column may comprise a casing tube and a steering spindle that is mounted in the casing tube so as to be rotatable about a longitudinal axis of the casing tube. Because the casing tube may be an outer casing tube that has a non-circular inner cross section and because an adaptor may be manufactured from metal as an extruded part and may comprise an outer circumferential configuration that is compatible with an inner cross section of the casing tube and an interior annular bearing seat, the adaptor can be inserted into the outer casing tube and can be fastened there.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 1, 2019
    Assignees: THYSSENKRUPP PRESTA AG, THYSSENKRUPP AG
    Inventors: Eric Gstöhl, Sven Hausknecht, Stefan-Hermann Loos, Frank Pasch, Christian Geissler
  • Patent number: 10403609
    Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Patent number: 10370023
    Abstract: A method may be used to produce a steering column for a motor vehicle that includes an inner steering column tube that receives a steering shaft such that the steering shaft is rotatable about its longitudinal axis, an outer steering column tube that receives the inner steering column tube and has a longitudinal slot that extends in a direction of the longitudinal axis, and a clamping apparatus that can be switched over between a release position in which the inner steering column tube is adjustable relative to the outer steering column tube and a fixing position in which the inner steering column tube is fixed relative to the outer steering column tube. The longitudinal slot may have a greater width in the release position than in the fixing position. The method may involve, amongst other steps, manufacturing at least one single blank of the outer steering column tube and/or of the inner steering column tube using an extrusion process.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 6, 2019
    Assignees: THYSSENKRUPP PRESTA AG, THYSSENKRUPP AG
    Inventors: Eric Gstöhl, Sven Hausknecht, Stefan-Hermann Loos, Frank Pasch, Christian Geissler
  • Patent number: 10373844
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 6, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
  • Patent number: 10347558
    Abstract: Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 9, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Christian Geissler, Georg Seidemann, Sonja Koller, Jan Proschwitz
  • Publication number: 20190206833
    Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.
    Type: Application
    Filed: December 23, 2015
    Publication date: July 4, 2019
    Inventors: Thorsten MEYER, Klaus REINGRUBER, Georg SEIDEMANN, Andreas WOLTER, Christian GEISSLER, Sven ALBERS
  • Publication number: 20190198455
    Abstract: A semiconductor apparatus comprises: a circuit board; a semiconductor package having a main surface, wherein the semiconductor package is arranged on the circuit board and the main surface faces the circuit board; a radio-frequency line element of the semiconductor package, which radio-frequency line element is arranged on the main surface or inside the semiconductor package, wherein the radio-frequency line element is designed to transmit a signal at a frequency of greater than 10 GHz; and an underfiller material arranged between the circuit board and the semiconductor package, wherein the radio-frequency line element and the underfiller material do not overlap in an orthogonal projection onto the main surface.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 27, 2019
    Inventors: Walter HARTNER, Christian GEISSLER, Thomas KILGER, Johannes LODERMEYER, Franz-Xaver MUEHLBAUER, Martin Richard NIESSNER, Claus WAECHTER
  • Patent number: 10301176
    Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel IP Corporation
    Inventors: Gerald Ofner, Thorsten Meyer, Reinhard Mahnkopf, Christian Geissler, Andreas Augustin