Abstract: An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.

Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.

Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.

Abstract: Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.

Abstract: A steering column may comprise a casing tube and a steering spindle that is mounted in the casing tube so as to be rotatable about a longitudinal axis of the casing tube. Because the casing tube may be an outer casing tube that has a non-circular inner cross section and because an adaptor may be manufactured from metal as an extruded part and may comprise an outer circumferential configuration that is compatible with an inner cross section of the casing tube and an interior annular bearing seat, the adaptor can be inserted into the outer casing tube and can be fastened there.

Abstract: A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

Abstract: An interconnect adaptor may be fabricated having a substantially planar surface, to which a microelectronic package may be electrically attached, and a non-planar surface with at least one interconnect extending from the interconnect adaptor planar surface to the interconnect adaptor non-planar surface. The interconnect adaptor non-planar surface may be shaped to substantially conform to a shape of a microelectronic substrate to which it may be attached, which eliminates the need to bend or otherwise adapt the microelectronic package to conform to the microelectronic substrate.

Abstract: Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.

Abstract: Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract: A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.

Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.