Patents by Inventor Christian Lavoie

Christian Lavoie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200243383
    Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Inventors: Huai Huang, Takeshi Nogami, Alfred Grill, Benjamin D. Briggs, Nicholas A. Lanzillo, Christian Lavoie, Devika Sil, Prasad Bhosale, James Kelly
  • Patent number: 10707167
    Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Patent number: 10707148
    Abstract: A field-effect transistor (FET) and method of manufacture thereof include patterning a mask above a source and drain of a FET to form holes in the mask, growing epitaxial structures from the holes in the mask, and growing a doped epitaxial shell to coat sidewalls of the epitaxial structures.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy Cohen, Christian Lavoie, Ahmet Serkan Ozcan, Paul Solomon
  • Patent number: 10685888
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie, Ahmet S. Ozcan
  • Publication number: 20200161436
    Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Guy M. Cohen, Paul M. Solomon, Christian Lavoie
  • Patent number: 10615261
    Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy M. Cohen, Paul M. Solomon, Christian Lavoie
  • Publication number: 20200058758
    Abstract: A method for forming a salicide includes forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape, forming a conductive material on the (111) facet, annealing the conductive material to form a silicide on the (111) facet, and forming at least one contact to the silicide.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Publication number: 20200035793
    Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
    Type: Application
    Filed: May 21, 2019
    Publication date: January 30, 2020
    Inventors: Guy M. Cohen, Paul M. Solomon, Christian Lavoie
  • Patent number: 10546941
    Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Publication number: 20200027820
    Abstract: A field-effect transistor (FET) and method of manufacture thereof include patterning a mask above a source and drain of a FET to form holes in the mask, growing epitaxial structures from the holes in the mask, and growing a doped epitaxial shell to coat sidewalls of the epitaxial structures.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Guy Cohen, Christian Lavoie, Ahmet Serkan Ozcan, Paul Solomon
  • Patent number: 10541191
    Abstract: A field-effect transistor (FET) and method of manufacture thereof include a gate, a doped semiconductor structure formed on top of the planar source and drain regions, and a sheath of conducting materials flanking the formed doped semiconductor structure, where the sheath is perpendicular to a surface of the planar source and drain regions.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy Cohen, Christian Lavoie, Ahmet Serkan Ozcan, Paul Solomon
  • Publication number: 20200006227
    Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Chao-Kun Hu, Christian Lavoie, Stephen M. Rossnagel, Thomas M. Shaw
  • Publication number: 20200006226
    Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Chao-Kun Hu, Christian Lavoie, Stephen M. Rossnagel, Thomas M. Shaw
  • Publication number: 20190348519
    Abstract: A semiconductor device includes epitaxially grown source/drain (S/D) regions each having a cross-sectional quadrilateral shape formed on a semiconductor fin on opposite sides of a transversely disposed gate structure. The S/D regions include top (111) facets on top halves of the cross-sectional quadrilateral shape. The device further includes a silicide formed on the top (111) facets.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 10461026
    Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chao-Kun Hu, Christian Lavoie, Stephen M. Rossnagel, Thomas M. Shaw
  • Patent number: 10453935
    Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Publication number: 20190288146
    Abstract: A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: International Business Machines Corporation
    Inventors: Joel P. De Souza, Harold John Hovel, Daniel Inns, Jeehwan Kim, Christian Lavoie, Devendra K. Sadana, Katherine L. Saenger, Davood Shahrjerdi, Zhen Zhang
  • Patent number: 10411101
    Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy M. Cohen, Paul M. Solomon, Christian Lavoie
  • Patent number: 10396229
    Abstract: A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joel P. De Souza, Harold J. Hovel, Daniel A. Inns, Jeehwan Kim, Christian Lavoie, Devendra K. Sadana, Katherine L. Saenger, Davood Shahrjerdi, Zhen Zhang
  • Patent number: 10304938
    Abstract: Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie