Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal element, a second transition metal liner including at least one second transition metal element that is different from the at least one first transition metal element and a metal contact are sequentially formed within each contact opening. Following a planarization process, the structure is annealed forming metal semiconductor alloy contacts at the bottom of each contact opening. Each metal semiconductor alloy contact that is formed includes the at least one first transition metal element, the at least one second transition metal element and a semiconductor element.

Abstract: A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin, the metal layer extends from the first diamond shaped epitaxial layer to the second diamond shaped epitaxial layer, the laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers, and the silicide layer takes on a crystal orientation of the first and the second epitaxial layers.

Abstract: A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a top portion of a silicon cap layer located in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin. The metal layer extends from the top portion of the silicon cap layer in direct contact with the first diamond shaped epitaxial layer to the top portion of the silicon cap layer in direct contact with the second diamond shaped epitaxial layer. The conducted laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers.

Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.

Abstract: Photovoltaic devices are formed with electroplated metal grids that are effectively adhered to the devices. Metal-rich silicides, such as nickel silicides, are formed on the devices by annealing. The metal used in the anneal exhibits low stress. Annealing may be conducted in ambient air followed by removal of oxide and excess metal from the metal-rich silicide. Laser patterning of the antireflective coating of the devices can be used to expose the emitter to form front grid contacts. Doping of the emitter in the patterned region can be increased during laser patterning. The ratio of the centerline to centerline pitch per laser width is controlled to ensure sufficient adhesion of subsequently plated busbars.

Abstract: Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.

Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.

Abstract: A contact can be formed by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material that exposes the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film having a first and second type of metal and a second metal film. The metal stack and the silicon-containing region of the semiconductor substrate are annealed to form a silicide that includes the first and second types of metal and that is in contact with the semiconductor substrate. A first liner is formed within the opening and a fill metal is deposited in the opening.

Abstract: Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.

Abstract: Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.

Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal element, a second transition metal liner including at least one second transition metal element that is different from the at least one first transition metal element and a metal contact are sequentially formed within each contact opening. Following a planarization process, the structure is annealed forming metal semiconductor alloy contacts at the bottom of each contact opening. Each metal semiconductor alloy contact that is formed includes the at least one first transition metal element, the at least one second transition metal element and a semiconductor element.

Abstract: A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

Abstract: Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.

Abstract: A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.

Abstract: A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality of vias disposed on the first substrate.

Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.

Abstract: A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide.

Abstract: A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.

Abstract: A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.

Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.