Patents by Inventor Christian Lavoie

Christian Lavoie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10304938
    Abstract: Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie
  • Publication number: 20190157187
    Abstract: A field-effect transistor (FET) and method of manufacture thereof include a gate, a pillar of grown on a top of the planar source and drain regions, and a conductive sheath flanking the pillar, the sheath is bent up, alongside, and over the gate.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Inventors: Guy Cohen, Christian Lavoie, Ahmet Serkan Ozcan, Paul Solomon
  • Patent number: 10147680
    Abstract: Various methods and semiconductor structures for fabricating at least one FET device having textured gate-source-drain contacts of the FET device that reduce or eliminate variability in parasitic resistance between the contacts of the FET device. An example fabrication method includes epitaxially growing a source-drain contact region on an underlying semiconductor substrate of one of a pFET device or an nFET device. The method deposits a bottom film layer directly on the epitaxially grown source-drain contact region. A first anneal forms a textured bottom silicide film layer directly on the epitaxially grown source-drain contact region. A top metal film layer is deposited on the textured bottom silicide film layer. A second anneal forms a textured top metal silicide film layer. The method can be repeated on the other one of the pFET device or the nFET device.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie, Jean L. Sweet
  • Publication number: 20180342392
    Abstract: In one aspect, a method for forming a doped III-V semiconductor material on a substrate includes the steps of: (a) forming a first monolayer on the substrate, wherein the first monolayer comprises at least one group III or at least one group V element; and (b) forming a doped second monolayer on a side of the first monolayer opposite the substrate, wherein the second monolayer comprises either i) at least one group V element if the first monolayer comprises at least one group III element, or ii) at least one group III element if the first monolayer comprises at least one group V element, wherein a dopant is selectively introduced only during formation of the second monolayer, and wherein steps (a) and (b) are performed using atomic layer epitaxy. Doped III-V semiconductor materials are also provided.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 29, 2018
    Inventors: Guy M. Cohen, Christian Lavoie
  • Publication number: 20180308951
    Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 25, 2018
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Publication number: 20180308952
    Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.
    Type: Application
    Filed: November 8, 2017
    Publication date: October 25, 2018
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Publication number: 20180300599
    Abstract: Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.
    Type: Application
    Filed: April 12, 2017
    Publication date: October 18, 2018
    Inventors: SHAWN P. FETTEROLF, JIN-PING HAN, CHRISTIAN LAVOIE, PAUL S. MCLAUGHLIN, AHMET S. OZCAN, ROGER A. QUON
  • Patent number: 10062567
    Abstract: In one aspect, a method for forming a doped III-V semiconductor material on a substrate includes the steps of: (a) forming a first monolayer on the substrate, wherein the first monolayer comprises at least one group III or at least one group V element; and (b) forming a doped second monolayer on a side of the first monolayer opposite the substrate, wherein the second monolayer comprises either i) at least one group V element if the first monolayer comprises at least one group III element, or ii) at least one group III element if the first monolayer comprises at least one group V element, wherein a dopant is selectively introduced only during formation of the second monolayer, and wherein steps (a) and (b) are performed using atomic layer epitaxy. Doped III-V semiconductor materials are also provided.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Christian Lavoie
  • Publication number: 20180226352
    Abstract: Various methods and semiconductor structures for fabricating at least one FET device having textured gate-source-drain contacts of the FET device that reduce or eliminate variability in parasitic resistance between the contacts of the FET device. An example fabrication method includes epitaxially growing a source-drain contact region on an underlying semiconductor substrate of one of a pFET device or an nFET device. The method deposits a bottom film layer directly on the epitaxially grown source-drain contact region. A first anneal forms a textured bottom silicide film layer directly on the epitaxially grown source-drain contact region. A top metal film layer is deposited on the textured bottom silicide film layer. A second anneal forms a textured top metal silicide film layer. The method can be repeated on the other one of the pFET device or the nFET device.
    Type: Application
    Filed: November 10, 2017
    Publication date: August 9, 2018
    Applicant: International Business Machines Corporation
    Inventors: Praneet ADUSUMILLI, Hemanth JAGANNATHAN, Christian LAVOIE, Jean L. SWEET
  • Publication number: 20180138093
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 17, 2018
    Inventors: Praneet ADUSUMILLI, Hemanth JAGANNATHAN, Christian LAVOIE, Ahmet S. OZCAN
  • Publication number: 20180122646
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 3, 2018
    Applicant: International Business Machines Corporation
    Inventors: Praneet ADUSUMILLI, Hemanth JAGANNATHAN, Christian LAVOIE, Ahmet S. OZCAN
  • Publication number: 20180090447
    Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 29, 2018
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Publication number: 20180083114
    Abstract: Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Praneet ADUSUMILLI, Hemanth JAGANNATHAN, Christian LAVOIE
  • Publication number: 20180068903
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Application
    Filed: October 26, 2016
    Publication date: March 8, 2018
    Inventors: Praneet ADUSUMILLI, Hemanth JAGANNATHAN, Christian LAVOIE, Ahmet S. OZCAN
  • Publication number: 20180068904
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Application
    Filed: October 26, 2016
    Publication date: March 8, 2018
    Applicant: International Business Machines Corporation
    Inventors: Praneet ADUSUMILLI, Hemanth JAGANNATHAN, Christian LAVOIE, Ahmet S. OZCAN
  • Publication number: 20180068857
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 8, 2018
    Inventors: Praneet ADUSUMILLI, Hemanth JAGANNATHAN, Christian LAVOIE, Ahmet S. OZCAN
  • Publication number: 20180061956
    Abstract: Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.
    Type: Application
    Filed: September 1, 2016
    Publication date: March 1, 2018
    Inventors: Praneet ADUSUMILLI, Hemanth JAGANNATHAN, Christian LAVOIE
  • Patent number: 9865546
    Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Publication number: 20180005939
    Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Chao-Kun Hu, Christian Lavoie, Stephen M. Rossnagel, Thomas M. Shaw
  • Patent number: 9837357
    Abstract: Various methods and semiconductor structures for fabricating at least one FET device having textured gate-source-drain contacts of the FET device that reduce or eliminate variability in parasitic resistance between the contacts of the FET device. An example fabrication method includes epitaxially growing a source-drain contact region on an underlying semiconductor substrate of one of a pFET device or an nFET device. The method deposits a Nickel film layer directly on the epitaxially grown source-drain contact region. A first anneal forms a textured Nickel silicide film layer directly on the epitaxially grown source-drain contact region. A second metal film layer is deposited on the textured Nickel silicide film layer. A second anneal forms a textured second metal silicide film layer. The method can be repeated on the other one of the pFET device or the nFET device.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie, Jean L. Sweet