Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.

Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.

Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.

Abstract: In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.

Abstract: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.

Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

Abstract: Various embodiments described below relate to an ESD protection device that includes a voltage controlled shunt (e.g., a transistor) to selectively shunt energy of an incoming ESD pulse away from a circuit that includes a semiconductor device to be protected. In some embodiments, the ESD protection device includes a power up detection element to determine whether the circuit has powered up. If the circuit is powered up, the power up detection element prevents inadvertent triggering of the ESD protection device.

Abstract: Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.

Abstract: Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.

Abstract: A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type.

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract: An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.

Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.