Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract: Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

Abstract: Various embodiments described below relate to an ESD protection device that includes a voltage controlled shunt (e.g., a transistor) to selectively shunt energy of an incoming ESD pulse away from a circuit that includes a semiconductor device to be protected. In some embodiments, the ESD protection device includes a power up detection element to determine whether the circuit has powered up. If the circuit is powered up, the power up detection element prevents inadvertent triggering of the ESD protection device.

Abstract: Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.

Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

Abstract: Various embodiments described below relate to an ESD protection device that includes a voltage controlled shunt (e.g., a transistor) to selectively shunt energy of an incoming ESD pulse away from a circuit that includes a semiconductor device to be protected. In some embodiments, the ESD protection device includes a power up detection element to determine whether the circuit has powered up. If the circuit is powered up, the power up detection element prevents inadvertent triggering of the ESD protection device.

Abstract: A semiconductor device including: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type adjacent to the first region; third and fourth semiconductor regions of the second conductivity type over or at least partially within the first semiconductor region; a fifth semiconductor region of the first conductivity type between the third and fourth semiconductor regions; a first gate over the fifth semiconductor region; sixth and seventh semiconductor regions of the first conductivity type over or at least partially within the second semiconductor region; an eighth semiconductor region of the second conductivity type between the sixth and seventh semiconductor regions; a second gate over the eighth semiconductor region; the third and seventh semiconductor regions coupled to first and second regions of the first gate, respectively, and the fourth and sixth semiconductor regions coupled to first and second regions of the second gate, respectively.

Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Abstract: An ESD protection element may include: a fin structure including a first connection region having a first conductivity type, a second connection region having a second conductivity type, first and second body regions formed between the connection regions, the first body region having the second conductivity type and formed adjacent to the first connection region, the second body region having the first conductivity type and formed adjacent to the second connection region, the body regions having a lower dopant concentration than the connection regions, a diffusion region formed between the body regions and having substantially the same dopant concentration as at least one of the first and second connection regions; a gate region on or above the first body region or the second body region; a gate control device electrically coupled to the gate region and configured to control at least one electrical potential applied to the gate region.

Abstract: Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit from an ESD event. The ESD protection device includes first and second trigger elements. Upon detecting an ESD pulse, the first trigger element provides a first trigger signal having a first pulse length. The second trigger element, upon detecting the ESD pulse, provides a second trigger signal having a second pulse length. The second pulse length is different from the first pulse length. A primary shunt shunts power of the ESD pulse away from the ESD susceptible circuit based on the first trigger signal. A current control element selectively pumps current due to the ESD pulse into a substrate of the primary shunt based on the second trigger signal.