Patents by Inventor Christoph Kadow

Christoph Kadow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9029941
    Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Markus Zundel, Christoph Kadow
  • Patent number: 8907418
    Abstract: A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface. The first and second trenches are disposed in parallel to each other. The semiconductor device further includes a first gate conductive line in contact with the gate electrodes in the first trenches, a second gate conductive line in contact with the gate electrodes in the second trenches, and a control element configured to control the potential applied to the second gate conductive line.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: December 9, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Noebauer, Christoph Kadow, Donald Dibra, Robert Illing
  • Publication number: 20140332881
    Abstract: A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface. The first and second trenches are disposed in parallel to each other. The semiconductor device further includes a first gate conductive line in contact with the gate electrodes in the first trenches, a second gate conductive line in contact with the gate electrodes in the second trenches, and a control element configured to control the potential applied to the second gate conductive line.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 13, 2014
    Inventors: Gerhard Noebauer, Christoph Kadow, Donald Dibra, Robert Illing
  • Publication number: 20140332877
    Abstract: A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element. The first transistor element includes first transistors, gate electrodes of which are disposed in first trenches in a first main surface of a semiconductor substrate. The second transistor element includes second transistors, gate electrodes of which are disposed in second trenches in the first main surface, and a second gate conductive line in contact with the gate electrodes in the second trenches. The control element is configured to control a potential applied to the second gate conductive line.
    Type: Application
    Filed: April 10, 2014
    Publication date: November 13, 2014
    Inventors: Gerhard Noebauer, Christoph Kadow, Donald Dibra, Robert Illing
  • Patent number: 8853786
    Abstract: A semiconductor device includes a semiconductor switching element and a rectifier element. The semiconductor switching element includes a plurality of switching cells connected in parallel between a first and a second load terminal and is formed in a cell area of a first semiconductor layer. The rectifier element includes a plurality of rectifier cells connected in parallel between the first load terminal and an auxiliary terminal. The rectifier cells are formed in a second semiconductor layer parallel to the first semiconductor layer in a vertical projection of the cell area. The semiconductor device may integrate free-wheeling diodes for inductive loads and semiconductor switching elements for switching the inductive loads.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: October 7, 2014
    Assignee: Infineon Technologies AG
    Inventor: Christoph Kadow
  • Publication number: 20140251408
    Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.
    Type: Application
    Filed: May 20, 2014
    Publication date: September 11, 2014
    Applicant: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow, Markus Zundel
  • Patent number: 8766394
    Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 1, 2014
    Assignee: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow, Markus Zundel
  • Publication number: 20140120673
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 1, 2014
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Patent number: 8643068
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Patent number: 8637954
    Abstract: A semiconductor die includes a substrate, a first device region and a second device region. The first device region includes an epitaxial layer on the substrate and one or more semiconductor devices of a first type formed in the epitaxial layer of the first device region. The second device region is spaced apart from the first device region and includes an epitaxial layer on the substrate and one or more semiconductor devices of a second type formed in the epitaxial layer of the second device region. The epitaxial layer of the first device region is different than the epitaxial layer of the second device region so that the one or more semiconductor devices of the first type are formed in a different epitaxial layer than the one or more semiconductor devices of the second type.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: January 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Wolfgang Werner, Christoph Kadow
  • Publication number: 20130307062
    Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.
    Type: Application
    Filed: July 24, 2013
    Publication date: November 21, 2013
    Inventors: Andreas Peter Meiser, Markus Zundel, Christoph Kadow
  • Patent number: 8519473
    Abstract: A vertical transistor component is produced by providing a semiconductor body with a first surface and a second surface, producing at least one gate contact electrode in a trench, the trench extending from the first surface through the semiconductor body to the second surface, and producing at least one gate electrode connected to the at least one gate contact electrode in the region of the first surface.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 27, 2013
    Assignee: Infineon Technologies AG
    Inventors: Andreas Peter Meiser, Markus Zundel, Christoph Kadow
  • Patent number: 8502307
    Abstract: An integrated circuit includes a semiconductor carrier including a first side and a second side opposite the first side. An FET is in a first area of the semiconductor carrier, and has a drain electrically coupled to a drain contact area at the first side and a source electrically coupled to a source contact area at the second side. First circuit elements are in a second area of the semiconductor carrier. The second area is electrically insulated from the semiconductor carrier surrounding the second area via a trench insulation extending through the semiconductor carrier from the first side to the second side. An interconnection level electrically interconnects the first circuit elements at the second side, and is electrically insulated from the source contact area in the entire second area via an insulating layer at the second side.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies AG
    Inventors: Christoph Kadow, Thorsten Meyer
  • Publication number: 20130187196
    Abstract: An integrated circuit includes a first and a second field effect transistor structure. The first field effect transistor structure includes a first gate electrode structure and a first field electrode structure. The second field effect transistor structure includes a second gate electrode structure and a second field electrode structure. The first and the second gate electrode structures are electrically separated from each other. The first and the second field electrode structures are separated from each other.
    Type: Application
    Filed: January 25, 2012
    Publication date: July 25, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Christoph Kadow
  • Publication number: 20130009252
    Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Christoph Kadow, Thorsten Meyer, Norbert Krischke
  • Patent number: 8319282
    Abstract: A bipolar transistor structure includes an epitaxial layer on a semiconductor substrate, a bipolar transistor device formed in the epitaxial layer and a trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor device. The trench structure includes a field plate spaced apart from the epitaxial layer by an insulating material. The bipolar transistor structure further includes a base contact connected to a base of the bipolar transistor device, an emitter contact connected to an emitter of the bipolar transistor device and isolated from the base contact and an electrical connection between the emitter contact and the field plate.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Christoph Kadow, Thorsten Meyer, Norbert Krischke
  • Publication number: 20120175687
    Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.
    Type: Application
    Filed: March 21, 2012
    Publication date: July 12, 2012
    Applicant: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow, Markus Zundel
  • Publication number: 20120126318
    Abstract: An integrated circuit includes a semiconductor carrier including a first side and a second side opposite the first side. An FET is in a first area of the semiconductor carrier, and has a drain electrically coupled to a drain contact area at the first side and a source electrically coupled to a source contact area at the second side. First circuit elements are in a second area of the semiconductor carrier. The second area is electrically insulated from the semiconductor carrier surrounding the second area via a trench insulation extending through the semiconductor carrier from the first side to the second side. An interconnection level electrically interconnects the first circuit elements at the second side, and is electrically insulated from the source contact area in the entire second area via an insulating layer at the second side.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Christoph Kadow, Thorsten Meyer
  • Patent number: 8169045
    Abstract: An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: May 1, 2012
    Assignee: Infineon Technologies AG
    Inventors: Donald Dibra, Christoph Kadow, Markus Zundel
  • Publication number: 20120098083
    Abstract: A semiconductor die includes a substrate, a first device region and a second device region. The first device region includes an epitaxial layer on the substrate and one or more semiconductor devices of a first type formed in the epitaxial layer of the first device region. The second device region is spaced apart from the first device region and includes an epitaxial layer on the substrate and one or more semiconductor devices of a second type formed in the epitaxial layer of the second device region. The epitaxial layer of the first device region is different than the epitaxial layer of the second device region so that the one or more semiconductor devices of the first type are formed in a different epitaxial layer than the one or more semiconductor devices of the second type.
    Type: Application
    Filed: October 25, 2010
    Publication date: April 26, 2012
    Applicant: INFINEON TECHNOLGIES AG
    Inventors: Thorsten Meyer, Wolfgang Werner, Christoph Kadow