Abstract: An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

Abstract: A method of gain calibration of an ADC stage is provided. The method includes steps of receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The the calibration signal may take any one of three values and may be constrained to one of only two of these three values. An ADC stage adapted to operate according to the method is also provided.

Abstract: A method of calibrating a pipelined analog to digital converter having a plurality of DAC elements and an additional calibration DAC element is provided. In the method as provided herein, a combination of positive, negative and zero reference voltages are applied to the element under calibration and positive and negative reference voltages are applied to the additional calibration DAC element to obtain four calibration states. An error of the DAC element under calibration is extracted by calculating an average of the difference between the four calibration states.

Abstract: A method of gain calibration of an ADC stage is disclosed. The method comprises receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The method is characterised in that the calibration signal may take any one of three values. In a preferred embodiment, the calibration is constrained to one of only two of these three values, when the input signal is in an outermost sub-range. An ADC stage adapted to operate according to the method is also disclosed.

Abstract: A method of calibrating a pipelined analog to digital converter (400) having a plurality of DAC elements (410) and an additional calibration DAC element (420), in which a combination of positive, negative and zero reference voltages to the element under calibration and positive and negative reference voltages to the additional calibration DAC element to obtain four calibration states from which an error of the element under calibration is extracted by calculating an average of the difference between the four calibration states.