Patents by Inventor Christopher H. Dick

Christopher H. Dick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10484012
    Abstract: A decoder circuit includes an input configured to receive an encoded message generated based on a QC-LDPC code. A first layer process unit is configured to process a first layer of a parity check matrix to generate a plurality of log-likelihood ratio (LLR) values corresponding to a plurality of variable nodes associated with the encoded message respectively. The first layer process unit includes a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values. A layer update unit is configured to generate a first LLR value for a first variable node using first and second row update values for the first variable node. An output is configured to provide a decoded message generated based the plurality of LLR values.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: November 19, 2019
    Assignee: XILINX, INC.
    Inventors: Nihat E. Tunali, Richard L. Walke, Christopher H. Dick
  • Publication number: 20190349312
    Abstract: A method, system, and computer program product that includes a processor assigning a network connection to an application, based upon the application requesting the network connection from a pool of network connections for connecting applications to a network resource, the assigned network connection for communicating a message with the network resource. The processor replaces the assigned network connection in the pool with a placeholder comprising configuration data of the assigned connection. The processor determined a period of inactivity of the assigned network connection, and the processor returns the assigned network connection to the pool, based upon the period reaching a defined threshold of inactivity.
    Type: Application
    Filed: July 10, 2019
    Publication date: November 14, 2019
    Inventors: Adrian D. Dick, Brian C. Homewood, Christopher Matthewson, Craig H. Stirling
  • Publication number: 20190303311
    Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Applicant: Xilinx, Inc.
    Inventors: Goran HK Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, Philip B. James-Roxby, Christopher H. Dick
  • Publication number: 20190303033
    Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Applicant: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Goran HK Bilski, Jan Langer, Baris Ozgul, Tim Tuan, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, Christopher H. Dick
  • Patent number: 10411656
    Abstract: A crest factor reduction (CFR) system includes a digital tilt filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilt filter output, where the CFR module is configured receive the digital tilt filter output signal and perform a CFR process to the digital tilt filter output signal to generate a CFR module output signal at a CFR module output. In addition, the CFR system may include a digital tilt equalizer coupled to the CFR module output, where the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: September 10, 2019
    Assignee: XILINX, INC.
    Inventors: Christopher H. Dick, Hongzhi Zhao, Hemang M. Parekh, Xiaohan Chen
  • Patent number: 10389652
    Abstract: A method, system, and computer program product that includes a processor assigning a network connection to an application, based upon the application requesting the network connection from a pool of network connections for connecting applications to a network resource, the assigned network connection for communicating a message with the network resource. The processor replaces the assigned network connection in the pool with a placeholder comprising configuration data of the assigned connection. The processor determined a period of inactivity of the assigned network connection, and the processor returns the assigned network connection to the pool, based upon the period reaching a defined threshold of inactivity.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Adrian D. Dick, Brian C. Homewood, Christopher Matthewson, Craig H. Stirling
  • Patent number: 10263644
    Abstract: Methods and systems are presented in this disclosure for implementing forward error correction in cloud and data center storage devices based on low-density parity-check (LDPC) channel coding. A forward error correction circuit presented herein includes a first LDPC decoder configured to perform hard-decision LDPC decoding of data read from a storage medium through a first read channel. The forward error correction circuit further includes a hybrid LDPC decoder selectively configurable to perform a selected one of hard-decision LDPC decoding and soft-decision LDPC decoding of data read from the storage medium through a second read channel, wherein, responsive to a control signal generated based, at least in part, on one or more parameters indicative of condition of the storage medium, the hybrid LDPC decoder is switchable between hard-decision LDPC decoding and soft-decision LDPC decoding.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 16, 2019
    Assignee: XILINX, INC.
    Inventors: Raied N. Mazahreh, Hai-Jo Tarn, Nihat E. Tunali, Christopher H. Dick
  • Patent number: 9973363
    Abstract: A method includes receiving frequency domain (FD) symbols associated with data symbols transmitted in a channel on a frame including a plurality of subcarriers and a plurality of time-slots. An equalization process is performed to the received FD symbols to generate FD equalized symbols. The FD equalized symbols is transformed to time domain (TD) symbols. A demodulation process is performed to the TD symbols to provide estimates of the data symbols.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 15, 2018
    Assignee: XILINX, INC.
    Inventors: Nihat E. Tunali, Michael Wu, Christopher H. Dick
  • Patent number: 9967057
    Abstract: A method includes communicating data in a channel. Received symbols for the data correspond to points of a received symbol space respectively. First and second dimensions of the received symbol space correspond to a real part and an imaginary part of the received symbols respectively. A first received symbol for the data is obtained. A first region of the received symbol space for the first received symbol is determined. A first regression model associated with the first region and a first bit of the first received symbol is retrieved from a storage. The first regression model includes a plurality of regressors. A first log-likelihood ratio (LLR) for the first bit of the first received symbol is estimated using the first regression model.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: May 8, 2018
    Assignee: XILINX, INC.
    Inventors: Nihat E. Tunali, Michael Wu, Hai-Jo Tarn, Christopher H. Dick
  • Patent number: 9941943
    Abstract: A system includes an integrated circuit configured to communicating data in a channel. A channel matrix for the channel including a plurality of columns is received. A preprocessing step is performed, using a preprocessing unit, to compute a plurality of preprocessed column values corresponding to respective columns. An update step is performed, using an update unit, to update an estimation vector using a plurality of outer-loop iterations of an outer loop. Each outer-loop iteration updates the estimation vector using the plurality of preprocessed column values. An access link process is performed using the estimation vector.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 10, 2018
    Assignee: XILINX, INC.
    Inventors: Michael Wu, Christopher H. Dick, Christoph E. Studer
  • Patent number: 9935604
    Abstract: An apparatus, and related method, relates generally to viable bandwidth filtering. In such an apparatus, an analysis filter bank has path filters associated with different bandwidths and is configured for filtering and transforming an input signal having a first bandwidth into a first interleaved output. A mask is coupled to the analysis filter bank and configured for masking at least one narrowband time signal of the first interleaved output. A synthesis filter bank is coupled to the mask. The synthesis filter bank is configured for transforming and filtering the masked first interleaved output to generate a second interleaved output for constructing an output signal having a second bandwidth. The second bandwidth is different than the first bandwidth for the variable bandwidth filtering.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: April 3, 2018
    Assignee: XILINX, INC.
    Inventors: Fredric J. Harris, Christopher H. Dick
  • Patent number: 9935810
    Abstract: A model identification system includes an analog to digital converter (ADC). The ADC includes a conversion circuit configured to receive a first analog signal and generate a first digital signal including samples having a first rate by sampling the first analog signal at the first rate. The ADC further includes a first digital signal processing (DSP) circuit configured to generate a second digital signal including samples having a second rate less than the first rate based on the second digital signal and a first sampling matrix. The first sampling matrix is a block diagonal matrix including a plurality of diagonal blocks, each diagonal block is a row vector including a plurality of elements.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: April 3, 2018
    Assignee: XILINX, INC.
    Inventors: Nikolaus H. Hammler, Christopher H. Dick
  • Patent number: 9876657
    Abstract: An integrated circuit (IC) includes a downlink unit including an input to receive a first plurality of frequency domain (FD) symbols associated with data symbols for a plurality of users, and an iteration unit to perform a plurality of iterations based on adjustment values. Each iteration includes generating a second plurality of FD symbols by performing a precoding process based on the first plurality of FD symbols, generating a third plurality of time domain (TD) symbols by performing a first modulation process based on the second plurality of FD symbols, generating a fourth plurality of TD symbols by performing a dynamic range reduction process based on absolute values of the third plurality of TD symbols, and updating the adjustment values. The downlink unit further includes a decision unit configured to generate transmit TD symbols for transmission through a channel to the plurality of users.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 23, 2018
    Assignee: XILINX, INC.
    Inventors: Charles Jeon, Christoph E. Studer, Michael Wu, Christopher H. Dick
  • Patent number: 9866269
    Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. The DPD system includes a first predistortion circuit configured to provide a first signal path coupled to the input to generate a first predistortion signal. The first predistortion circuit includes a first infinite impulse response (IIR) filter. A second predistortion circuit is configured to provide a second signal path coupled to the input in parallel with the first signal path to generate a second predistortion signal. The second predistortion circuit includes a second IIR filter. A combiner circuit is configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: January 9, 2018
    Assignee: XILINX, INC.
    Inventors: Hongzhi Zhao, Christopher H. Dick, Hemang M. Parekh
  • Patent number: 9787289
    Abstract: Disclosed is apparatus and method to filter a signal. In such an apparatus, an outer polyphase filter is configured for receiving an input signal and for channelizing the input signal into outer filtered samples. An outer Inverse Fourier Transform block is coupled to the outer polyphase filter and configured for transforming the outer filtered samples into a coarse multi-path output. An inner polyphase filter is coupled to a path of the coarse multi-path output for receiving information therefrom and configured for generating inner filtered samples of the information obtained from the path. The inner filtered samples are for moving an edge of a passband associated with the outer filtered samples toward a center of the passband.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: October 10, 2017
    Assignee: XILINX, INC.
    Inventors: Fredric J. Harris, Christopher H. Dick
  • Patent number: 9727416
    Abstract: An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed. The decoded data is provided as soft decisions representing probabilities of the decoded data. The memory controller is for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 8, 2017
    Assignee: XILINX, INC.
    Inventor: Christopher H. Dick
  • Patent number: 9590567
    Abstract: An apparatus relates generally to preconditioning an input signal. In this apparatus, a first digital predistortion module and a second digital predistortion module are for receiving the input signal for respectively providing a first predistorted signal and a second predistorted signal. A combiner is for combining the first predistorted signal and the second predistorted signal for providing an output signal. The first digital predistortion module includes a moving mean block for receiving the input signal for providing a moving mean signal. The first digital predistortion module further includes a digital predistorter for receiving the input signal and the moving mean signal for providing the first predistorted signal.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: March 7, 2017
    Assignee: XILINX, INC.
    Inventors: Hongzhi Zhao, Christopher H. Dick
  • Publication number: 20170012596
    Abstract: Disclosed is apparatus and method to filter a signal. In such an apparatus, an outer polyphase filter is configured for receiving an input signal and for channelizing the input signal into outer filtered samples. An outer Inverse Fourier Transform block is coupled to the outer polyphase filter and configured for transforming the outer filtered samples into a coarse multi-path output. An inner polyphase filter is coupled to a path of the coarse multi-path output for receiving information therefrom and configured for generating inner filtered samples of the information obtained from the path. The inner filtered samples are for moving an edge of a passband associated with the outer filtered samples toward a center of the passband.
    Type: Application
    Filed: July 6, 2015
    Publication date: January 12, 2017
    Applicant: Xilinx, Inc.
    Inventors: Fredric J. Harris, Christopher H. Dick
  • Publication number: 20170012598
    Abstract: An apparatus, and related method, relates generally to viable bandwidth filtering. In such an apparatus, an analysis filter bank has path filters associated with different bandwidths and is configured for filtering and transforming an input signal having a first bandwidth into a first interleaved output. A mask is coupled to the analysis filter bank and configured for masking at least one narrowband time signal of the first interleaved output. A synthesis filter bank is coupled to the mask. The synthesis filter bank is configured for transforming and filtering the masked first interleaved output to generate a second interleaved output for constructing an output signal having a second bandwidth. The second bandwidth is different than the first bandwidth for the variable bandwidth filtering.
    Type: Application
    Filed: July 6, 2015
    Publication date: January 12, 2017
    Applicant: Xilinx, Inc.
    Inventors: Fredric J. Harris, Christopher H. Dick
  • Publication number: 20170005627
    Abstract: An apparatus relates generally to preconditioning an input signal. In this apparatus, a first digital predistortion module and a second digital predistortion module are for receiving the input signal for respectively providing a first predistorted signal and a second predistorted signal. A combiner is for combining the first predistorted signal and the second predistorted signal for providing an output signal. The first digital predistortion module includes a moving mean block for receiving the input signal for providing a moving mean signal. The first digital predistortion module further includes a digital predistorter for receiving the input signal and the moving mean signal for providing the first predistorted signal.
    Type: Application
    Filed: July 2, 2015
    Publication date: January 5, 2017
    Applicant: Xilinx, Inc.
    Inventors: Hongzhi Zhao, Christopher H. Dick