Abstract: A tunable narrow-band filter that includes a sigma-delta modulator. In one embodiment, a conventional DC canceler is modified to include a re-quantizer in the feedback loop in the form of a ?? modulator. In another embodiment, a digital receiver employs a processing chip, such as an FPGA, that includes a ?? modulator to requantize oversampled control signals in the digital receiver. In still another embodiment, a wide-bandwidth sigma-delta loop has a tunable center frequency.

Abstract: A narrow-band bandpass filter is implemented in a field programmable gate array (FPGA). An analog-to-digital converter quantizes an input analog signal with a high degree of precision to produce input data samples. A sigma-delta modulator re-quantizes the samples with a substantially lower degree of precision. The re-quantized samples are passed through a bandpass, lowpass, or highpass, finite impulse response (FIR) filter which operates at the lower degree of precision. The reduced degree of precision enables a substantial reduction in the number of resources required to implement the narrow-band bandpass, lowpass, or highpass filter in the FPGA. The modulator includes a predictor filter which has a center frequency coinciding with that of the FIR filter, and redistributes noise such that it is lowest within the passband of the FIR filter. The narrow-band filter design can be adapted to incorporate a single or multi-rate decimator configuration.

Abstract: A circuit arrangement and method for performing the 2-D DCT. An input permutation processor reorders input samples, constructing a logical matrix of input samples. A plurality of 1-D DCT processors are arranged to receive the reordered data and apply the 1-D DCT along extended diagonals of the matrix. The output polynomials from the 1-D DCT processors are provided to a polynomial transform processor, and the output data from the polynomial transform processor are reordered, by an output permutation processor. The 1-D DCT processors and polynomial transform are multiplier free, thereby minimizing usage of FPGA resources in an FPGA implementation.

Abstract: A circuit arrangement and method for direct digital synthesis (DDS). In various embodiments, the invention feeds forward the phase error introduced by a quantizer in a DDS system. The error is fed forward to adjust the sine and cosine values that are obtained based on output from the quantizer. Correction of the sine and cosine values based on the fed-forward error values results in a significant reduction in the effect of spectral artifacts.

Abstract: An FPGA configured for computation of an N.times.N discrete Fourier transform (DFT) using polynomial transforms defined in modified rings of transforms, comprising a first buffer for ordering a set of polynomial data in a two dimensional matrix, a multiplier for multiplying each element of the two dimensional matrix by .omega..sup.-n.sbsp.2 (where .omega.=e.sup.-j.pi./N, e is a constant (ln(e)=1),j=.sqroot.-1, n.sub.2 =the column index number in the matrix, and N=the transform length) to produce a premultiplication product, a polynomial transform circuit for performing a polynomial transform (PT) modulo (z.sup.N +1), size N, root z.sup.2 on the premultiplication product to produce a polynomial transform result, where z represents the unit delay operator, a reduced DFT calculator for performing N reduced DFTs of N terms on the polynomial transform result to produce a permuted output, and an address generator for reordering the permuted output to a natural order.