Abstract: A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.

Abstract: A fin field effect transistor (FinFET) device includes a substrate and a template material over the substrate. The template material absorbs lattice mismatches with the substrate. The FinFET device also includes a barrier material over the template material. The barrier material is free of point defects. The FinFET device further includes a channel material over the barrier material.

Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A structure includes a substrate, a template layer, a barrier layer, and a device layer. The substrate comprises a first crystalline material. The template layer comprises a second crystalline material, and the second crystalline material is lattice mismatched to the first crystalline material. The template layer is over and adjoins the first crystalline material, and the template layer is at least partially disposed in an opening of a dielectric material. The barrier layer comprises a third crystalline material, and the third crystalline material is a binary III-V compound semiconductor. The barrier layer is over the template layer. The device layer comprises a fourth crystalline material, and the device layer is over the barrier layer.

Abstract: A method comprises growing a channel layer comprising a first channel region and a second channel region, depositing a first hard mask layer over the channel layer, patterning the first hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, depositing a first cap layer over the first delta doping layer, depositing a second hard mask layer over the channel layer, wherein the first cap layer is embedded in the second hard mask layer, patterning the second hard mask layer and the first hard mask layer to expose the second channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region and applying a first diffusion process to the first delta doping layer and the second delta doping layer.

Abstract: The present disclosure provides a method of forming a fin-like field-effect transistor (FinFET) device. The method includes forming a first strain-relaxed buffer (SRB) stack over a substrate. The first SRB stack has a lattice mismatch with respect to the substrate that generates a threading dislocation defect feature in the first SRB stack. The method also includes forming a patterned dielectric layer over the first SRB stack. The patterned dielectric layer includes a trench extending therethrough. The method also includes forming a second SRB stack over the first SRB stack and within the trench. The second SRB stack has a lattice mismatch with respect to the substrate such that an upper portion of the second SRB stack is without threading dislocation defects.

Abstract: Methods of forming semiconductor devices and fin field effect transistors (FinFETs), and FinFET devices, are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a barrier material comprising AlInAsSb over a substrate, and forming a channel material of a transistor over the barrier layer.

Abstract: Semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a representative semiconductor device includes a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less, and a group III-V material over the group III material.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.

Abstract: A computer security threat sharing technology is described. A computer security threat is recognized at an organization. A partner network graph is queried for security nodes connected to a first security node representing the organization. The first security node is connected to at least a second security node representing a trusted security partner of the organization. The second security node is associated with identification information. The computer security threat recognized by the organization is communicated to the trusted security partner using the identification information associated with the second security node.

Abstract: A method includes annealing a silicon region in an environment including hydrogen (H2) and hydrogen chloride (HCl) as process gases. After the step of annealing, a semiconductor region is grown from a surface of the silicon region.

Abstract: Methods of forming semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less. The method includes forming a group III-V material over the group III material.

Abstract: A device includes a clamp and a sensor. The sensor can be permanently attached to the clamp and tissue by the force exerted by the clamp. The clamp includes a first jaw member and a second jaw member. The first jaw member has a jaw face and the second jaw member has a complementary face. The second jaw member is held in alignment with the first jaw member by a joint. The joint has an elastic member configured to exert a compressive force between the jaw face and the complementary face. The joint is configured to allow movement of the jaw face relative to the complementary face in directions corresponding to pitch, roll, yaw, and heave. The compressive force is distributed over a surface of the jaw face. The sensor is coupled to the jaw face or held in place by the compressive force of the jaw face. The sensor is configured to generate a sensor signal corresponding to a physiological parameter of tissue proximate the jaw face.

Abstract: A technology is described for a salt service. An example method may include generating a salt value and a salt identifier used to reference the salt value in response to a salt value setup request. Storing the salt value in a data store where the salt value may be referenced by the salt identifier. The salt value and the salt identifier may then be provided in response to the salt value setup request to enable the salt identifier to be stored in association with a first hash value generated from the salt value and a customer password for future customer authentications. In response to an authentication request, the salt value may be retrieved from the data store and the salt value may be provided, enabling customer authentication to be performed by comparing the first hash value with a second hash value generated from the salt value and a customer password.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.

Abstract: A thin-sheet non-planar circuit device such as a FinFET and a method for forming the device is disclosed. In some exemplary embodiments, the device includes a substrate having a top surface and a feature disposed on the substrate that extends above the top surface. A material layer disposed on the feature. The material layer includes a plurality of source/drain regions and a channel region disposed between the source/drain regions. A gate stack is disposed on the channel region of the material layer. In some such embodiments, the feature includes a plurality of side surfaces, and the material layer is disposed on each of the side surface surfaces. In some such embodiments, the feature also includes a top surface and the material layer is further disposed on the top surface. In some embodiments, the top surface of the feature is free of the material layer.

Abstract: Integrated circuit devices having FinFETs with channel regions low in crystal defects and current-blocking layers underneath the channels to improve electrostatic control. Optionally, an interface control layer formed of a high bandgap semiconductor is provided between the current-blocking layer and the channel. The disclosure also provides methods of forming integrated circuit devices having these structures. The methods include forming a FinFET fin including a channel by epitaxial growth, then oxidizing a portion of the fin to form a current-blocking layer.

Abstract: A method comprises growing a channel layer comprising a first channel region and a second channel region, depositing a first hard mask layer over the channel layer, patterning the first hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, depositing a first cap layer over the first delta doping layer, depositing a second hard mask layer over the channel layer, wherein the first cap layer is embedded in the second hard mask layer, patterning the second hard mask layer and the first hard mask layer to expose the second channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region and applying a first diffusion process to the first delta doping layer and the second delta doping layer.

Abstract: Methods of forming semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less. The method includes forming a group III-V material over the group III material.

Abstract: Methods of forming semiconductor devices and fin field effect transistors (FinFETs), and FinFET devices, are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a barrier material comprising AlInAsSb over a substrate, and forming a channel material of a transistor over the barrier layer.

Abstract: A method comprises growing a channel layer over a substrate, wherein the channel layer comprises a first channel region and a second channel region, and wherein the first channel region and the second channel region are separated by a first isolation region, depositing a hard mask layer over the channel layer, patterning the hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region, wherein the second delta doping layer is of a different doping density from the first delta doping layer and applying a diffusion process to the first delta doping layer and the second delta doping layer.