Patents by Inventor Christopher J. Petti

Christopher J. Petti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11101326
    Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: August 24, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
  • Patent number: 11088206
    Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 10, 2021
    Assignee: SanDisk Tehnologies LLC
    Inventors: Federico Nardi, Christopher J Petti, Gerrit Jan Hemink
  • Patent number: 11031059
    Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: June 8, 2021
    Assignee: Sandisk Technologies LLC
    Inventors: Christopher J. Petti, Tz-Yi Liu, Ali Al-Shamma, Yoocharn Jeon
  • Patent number: 10957680
    Abstract: Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 23, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Masanori Tsutsumi, Sayako Nagamine, Yuji Fukano, Akio Nishida, Christopher J. Petti
  • Publication number: 20200388332
    Abstract: A method is provided that includes applying a read voltage to a resistance-switching memory cell to determine a first memory cell resistance, applying a first write voltage to the resistance-switching memory cell, applying the read voltage to the resistance-switching memory cell to determine a second memory cell resistance, and comparing the first memory cell resistance to the second memory cell resistance to determine that the resistance-switching memory cell is in a first memory state or a second memory state.
    Type: Application
    Filed: July 3, 2019
    Publication date: December 10, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Michael K. Grobis, Daniel Bedau, Christopher J. Petti
  • Publication number: 20200342926
    Abstract: A memory array is provided that includes a first memory level including a plane of first selector material, and a plurality of first memory cells each including a corresponding first magnetic memory element coupled in series with a corresponding first selector element. Each first selector element includes a region of the plane of first selector material.
    Type: Application
    Filed: April 28, 2019
    Publication date: October 29, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Jordan A. Katine, Mac D. Apodaca, Christopher J. Petti
  • Publication number: 20200303459
    Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Federico Nardi, Christopher J. Petti, Gerrit Jan Hemink
  • Publication number: 20200273512
    Abstract: Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Inventors: Christopher J. Petti, Tz-Yi Liu, Ali Al-Shamma, Yoocharn Jeon
  • Publication number: 20200258572
    Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of isolation elements coupled between the vertically-oriented bit lines and the global bit lines. Each isolation element includes a vertical thin-film transistor and a threshold selector device.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 13, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Abhijit Bandyopadhyay, Christopher J. Petti, Brian Le
  • Patent number: 10741585
    Abstract: A content addressable memory cell is provided that includes a vertical transistor having a gate oxide that includes a ferroelectric material.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 11, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Christopher J. Petti
  • Patent number: 10734073
    Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of isolation elements coupled between the vertically-oriented bit lines and the global bit lines. Each isolation element includes a vertical thin-film transistor and a threshold selector device.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Abhijit Bandyopadhyay, Christopher J. Petti, Brian Le
  • Publication number: 20200243486
    Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.
    Type: Application
    Filed: January 29, 2020
    Publication date: July 30, 2020
    Applicant: Sunrise Memory Corporation
    Inventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
  • Publication number: 20200227397
    Abstract: Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventors: Shinsuke YADA, Masanori TSUTSUMI, Sayako NAGAMINE, Yuji FUKANO, Akio NISHIDA, Christopher J. PETTI
  • Patent number: 10714534
    Abstract: A method is provided that includes forming a memory cell that includes a memory element coupled in series with an isolation element. The isolation element includes a vertical thin-film transistor and a threshold selector device.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: July 14, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Abhijit Bandyopadhyay, Christopher J. Petti, Brian Le
  • Publication number: 20200075631
    Abstract: A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Yingda Dong, James Kai, Christopher J. Petti
  • Publication number: 20200006383
    Abstract: A content addressable memory cell is provided that includes a vertical transistor having a gate oxide that includes a ferroelectric material.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventor: Christopher J. Petti
  • Patent number: 10453531
    Abstract: A content addressable memory element is provided that includes a vertical transistor including a first electrode coupled to a match line, a second electrode coupled to a ground line, a first gate electrode coupled to a search line, and a second gate electrode coupled to a complementary search line. The first gate electrode and the second gate electrode are disposed on opposite sides of the vertical transistor, and the vertical transistor includes a charge storage memory element.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 22, 2019
    Assignee: SanDisk Technologies LLC
    Inventor: Christopher J. Petti
  • Patent number: 10388646
    Abstract: A surge protection device contains a first electrode, a second electrode electrically connected to electrical ground, and a field-induced switching component electrically contacting the first electrode and the second electrode. The field-induced switching component can include a correlated-electron material or a volatile conductive bridge.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: August 20, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Derek Stewart, Daniel Bedau, Michael Grobis, Christopher J. Petti
  • Patent number: 10381409
    Abstract: Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Raghuveer S. Makala, Christopher J. Petti, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang
  • Patent number: 10381559
    Abstract: Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 13, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Fei Zhou, Raghuveer S. Makala, Christopher J. Petti, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang