Patents by Inventor Christopher J. Petti

Christopher J. Petti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8129613
    Abstract: Fabrication of a photovoltaic cell comprising a thin semiconductor lamina may require additional processing after the semiconductor lamina is bonded to a receiver. To minimize high-temperature steps after bonding, the p-n junction is formed at the back of the cell, at the bonded surface. In some embodiments, the front surface of the semiconductor lamina is not doped or is locally doped using low-temperature methods. The base resistivity of the photovoltaic cell may be reduced, allowing a front surface field to be reduced or omitted.
    Type: Grant
    Filed: August 10, 2008
    Date of Patent: March 6, 2012
    Assignee: Twin Creeks Technologies, Inc.
    Inventors: Mohamed M. Hilali, Christopher J. Petti
  • Patent number: 8107270
    Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: January 31, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti
  • Patent number: 8101451
    Abstract: A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to a rigid or semi-rigid pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element; such adhesives may be unable to tolerate processing temperatures and conditions required to complete the device.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: January 24, 2012
    Assignee: Twin Creeks Technologies, Inc.
    Inventors: Venkatesan Murali, Christopher J Petti, Theodore Smick, Mohamed M Hilali, Kathy J Jackson, Zhiyong Li, Gopalakrishna Prabhu
  • Publication number: 20110306177
    Abstract: A method is described for reducing dielectric overetch. The method includes: (1) forming a substantially planar surface that coexposes conductive or semiconductor features and a dielectric etch stop layer, the conductive or semiconductor features including pillars that each include a vertically oriented diode; (2) depositing second dielectric fill directly on the planar surface; and (3) etching a void in the second dielectric fill, wherein the etch is selective between the second dielectric fill and the dielectric etch stop layer, wherein the etch stops on the dielectric etch stop layer. Numerous other aspects are provided.
    Type: Application
    Filed: August 23, 2011
    Publication date: December 15, 2011
    Inventors: Samuel V. Dunton, Christopher J. Petti, Usha Raghuram
  • Patent number: 8008187
    Abstract: A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: August 30, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Samuel V. Dunton, Christopher J. Petti, Usha Raghuram
  • Patent number: 8004013
    Abstract: A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: August 23, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Christopher J Petti, S. Brad Herner
  • Publication number: 20110189840
    Abstract: In a first aspect, a method is provided that includes: forming a plurality of conductive or semiconductive features above a first dielectric material; depositing a second dielectric material above the conductive or semiconductive features; etching a void in the second dielectric material, wherein the etch is selective between the first and the second dielectric material and the etch stops on the first dielectric material; and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.
    Type: Application
    Filed: April 15, 2011
    Publication date: August 4, 2011
    Inventor: Christopher J. Petti
  • Patent number: 7982273
    Abstract: A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: July 19, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Christopher J. Petti, Steven J. Radigan, Tanmay Kumar
  • Publication number: 20110162688
    Abstract: A novel surface texturing provides improved light-trapping characteristics for photovoltaic cells. The surface is asymmetric and includes shallow slopes at between about 5 and about 30 degrees from horizontal as well as steeper slopes at about 70 degrees or more from horizontal. It is advantageously used as either the front or back surface of a thin semiconductor lamina, for example between about 1 and about 20 microns thick, which comprises at least the base or emitter of a photovoltaic cell. In embodiments of the present invention, the shallow slopes are formed using imprint photolithography.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 7, 2011
    Applicant: TWIN CREEKS TECHNOLOGIES, INC.
    Inventor: Christopher J. Petti
  • Publication number: 20110156044
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 30, 2011
    Applicant: SanDisk 3D LLC
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher J. Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald, Brad Herner
  • Patent number: 7964431
    Abstract: A photovoltaic cell is formed by bonding a donor body to a receiver element and cleaving a thin lamina from the donor body. Electrical contact is made to the bonded surface of the lamina through vias formed in the lamina. In some embodiments the emitter exists only at the bonded surface or only at the cleaved surface face; the emitter does not wrap through the vias between the surfaces. Wiring contacting each of the two surfaces is formed only at the cleaved face, and one set of wiring contacts the bonded surface through conductive material formed in the vias, insulated from the via sidewalls.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: June 21, 2011
    Assignee: Twin Creeks Technologies, Inc.
    Inventors: Christopher J Petti, Mohamed M Hilali
  • Publication number: 20110095438
    Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
    Type: Application
    Filed: October 26, 2010
    Publication date: April 28, 2011
    Applicant: SANDISK 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Publication number: 20110095338
    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
    Type: Application
    Filed: October 26, 2010
    Publication date: April 28, 2011
    Applicant: SANDISK 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Patent number: 7927990
    Abstract: A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 19, 2011
    Assignee: SanDisk Corporation
    Inventors: Kang-Jay Hsia, Calvin K Li, Christopher J Petti
  • Patent number: 7928007
    Abstract: In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: April 19, 2011
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Publication number: 20110073175
    Abstract: A photovoltaic cell is described having emitter portions formed at both a light-facing surface and a back surface of the cell. In some embodiments, heavily doped emitter regions extend between the front and back emitter regions, connecting them electrically. Use of this structure is particularly well-adapted to a cell formed by implanting a semiconductor donor body with hydrogen and/or helium ions, affixing the donor body to a receiver element, cleaving a lamina from the donor body, and completing fabrication of a photovoltaic cell comprising the lamina. The emitter portion formed at the unbonded surface may comprise amorphous silicon. The lamina may be thin, for example 10 microns thick or less.
    Type: Application
    Filed: September 29, 2009
    Publication date: March 31, 2011
    Applicant: TWIN CREEKS TECHNOLOGIES, INC.
    Inventors: Mohamed M. Hilali, Christopher J. Petti
  • Patent number: 7915522
    Abstract: A novel surface texturing provides improved light-trapping characteristics for photovoltaic cells. The surface is asymmetric and includes shallow slopes at between about 5 and about 30 degrees from horizontal as well as steeper slopes at about 70 degrees or more from horizontal. It is advantageously used as either the front or back surface of a thin semiconductor lamina, for example between about 1 and about 20 microns thick, which comprises at least the base or emitter of a photovoltaic cell. In embodiments of the present invention, the shallow slopes are formed using imprint photolithography.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Twin Creeks Technologies, Inc.
    Inventor: Christopher J. Petti
  • Patent number: 7888200
    Abstract: In some aspects, a method of forming a memory circuit is provided that includes (1) forming a two-terminal memory element on a substrate between a gate layer and a first metal layer of the memory circuit; and (2) forming a CMOS transistor on the substrate, the CMOS transistor for programming the two-terminal memory element. Numerous other aspects are provided.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: February 15, 2011
    Assignee: Sandisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 7887999
    Abstract: Methods of making pillar shaped device array using a triple or quadruple exposure technique are described. A plurality of pillar shaped devices are formed arranged in a hexagonal or rectangular pattern.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: February 15, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti
  • Patent number: 7868388
    Abstract: In some aspects, a memory circuit is provided that includes (1) a two-terminal memory element formed on a substrate; and (2) a CMOS transistor formed on the substrate and adapted to program the two-terminal memory element. The two-terminal memory element is formed between a gate layer and a first metal layer of the memory circuit. Numerous other aspects are provided.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: January 11, 2011
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti