Abstract: An error detection and correction system is disclosed for efficiently processing a product code typically employed in an optical storage device. In particular, the present invention decreases the processing time associated with iteratively processing the rows and columns of the product code by processing only those code words that were "flagged" during a previous iteration. If, for example, while processing the column code words a byte in a column code word is corrected, then the corresponding intersecting row code word is flagged for processing during the "row pass." Only the row code words that have been flagged are processed during the "row pass", which significantly reduces buffer access latency and increases the overall throughput of the storage system. To assist in error detection and correction, an array of erasure pointers is employed where each erasure pointer corresponds to a byte in a code word.

Abstract: A disc drive storage system having a plurality of data tracks and data sectors within each track, wherein each track further comprises a redundancy sector for reconstructing a data sector unrecoverable at the sector level. The latency of the storage system is minimized by generating track level redundancy data over the write range of data sectors and storing the "write" redundancy to the redundancy sector. Then during idle time of the storage system, the track level redundancy is regenerated for the entire track. If an unrecoverable data sector is encountered during the idle time redundancy regeneration, and the unrecoverable data sector is within the write range of the previous write operation, then it is reconstructed using the track level redundancy data stored in the redundancy sector.

Abstract: A disc storage system comprising a sector level ECS for correcting errors within a sector during readback, and a track level ECS for correcting a sector that becomes unrecoverable at the sector level either because the number of hard errors exceeds the error correction capability of the sector redundancy, or because the sector is unreadable due, for instance, to an inability to synchronize to the sector data. A data buffer stores the data sectors, and a redundancy buffer stores the track level redundancy data. If during a read operation a data sector is determined to be unrecoverable using the sector level redundancy, the storage system corrects the unrecoverable sector using the track level redundancy.

Abstract: A magnetic disk storage system is disclosed wherein byte synchronization to sector data is achieved even when noise in the read channel, due for instance to a thermal asperity (TA), corrupts the primary preamble and/or sync mark fields or causes a loss of frequency or phase lock. The data sector format is modified to comprise at least one secondary sync mark in addition to the conventional primary sync mark recorded at the beginning of the data field. In this manner, when the primary sync mark becomes undetectable due to errors, or when byte synchronization is lost, the storage system can still synchronize to the data sector using the secondary sync mark. The secondary sync mark is preferably spaced apart from the primary sync mark with either a gap (no data) or user data inserted inbetween.

Abstract: A rate 16/17 ENDEC is disclosed which encodes 16 bit input data words into 17 bit codewords according to at least one predetermined code constraint, such as an RLL (d,k) constraint. The encoder encodes the high and low byte of the input data word using the same mapping circuitry which reduces its cost and complexity. The codewords are transferred through a communication channel, such as a computer disc storage device, and upon reception (or readback) the first 8 bits of the 17 bit codeword are decoded independent from the last 8 bits which prevents error propagation. That is, the first 8 bits of the codeword are decoded into a high byte of the decoded data word, and the last 8 bits of the codeword are decoded into a low byte of the decoded data word independent from one another.

Abstract: A partial response class-IV (PR4) read channel is disclosed for magnetic recording including a coding scheme which improves timing recovery by providing a more accurate phase error estimate. The conventional 1/(1+D.sup.2) precoder is not used in the present invention (to avoid the ambiguous initial state), so that the read channel can directly control the flux transitions written onto the magnetic disc. This enables the read channel to encode user data according to a criteria that creates well defined slopes in the analog read signal at the sample instances, thereby improving the accuracy of the timing recovery phase error estimate.

Abstract: An apparatus and method of generating redundancy symbols and syndromes which is order-programmable is disclosed. The apparatus and method involves the implementation of an error correcting encoder/decoder for polynomial codes which uses a single circuit to generate check symbols during the transmit operation and to generate syndromes during a receive operation. The selection of roots for the code generator, and hence, the code order is programmable.

Abstract: A sampled amplitude read channel incorporated within a magnetic disk storage system for reading data recorded in concentric tracks on a magnetic medium, where the data comprises user data sectors recorded at varying data rates across a plurality of predefined zones and embedded servo data sectors recorded at the same data rate across the zones. The sampled amplitude read channel comprises a timing recovery component for synchronous sampling of a read signal from a magnetic read head positioned over the magnetic medium, a gain control component for adjusting the amplitude of the read signal, and a DC offset component for cancelling a DC offset in the read signal. These components are dynamically configured to operate according to whether the read channel is processing user data or embedded servo data.

Abstract: A sampled amplitude read channel reads data from a magnetic medium by detecting digital data from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a read head positioned over the magnetic medium. The digital data comprises a preamble field followed by a sync mark followed by a data field. Timing recovery in the read channel synchronizes to a phase and frequency of the preamble field and a sync detector detects the sync mark in order to frame operation of an RLL decoder for decoding the detected data field. To decrease the probability of early misdetection, the sync mark is chosen to have minimum correlation with shifted versions of the sync mark concatenated with the preamble field. To further increase the fault tolerance, the sync mark detector is enabled by timing recovery relative to the end of the preamble field.

Abstract: A PR4 sampled amplitude read channel is disclosed which employs an NRZI modulator for writing encoded user data directly to a magnetic disc storage medium instead of using a conventional 1/(1+D.sup.2) precoder. This avoids the ambiguous initial state of the precoder and allows the read channel to directly control the magnetic flux transitions written onto the disc. Upon read back, a PR4 sequence detector outputs a preliminary data sequence which is converted back into the NRZI domain and then decoded into an estimated user data sequence.

Abstract: An asynchronous data path controller for reading, correcting, and transferring data on-the-fly from a digital recording device to a host system. Central to the data path controller is a RAM for storing the data as it is read from the recording device and a RAM controller for arbitrating access to the RAM. An error correcting system reads the data from the RAM, corrects the data, and then restores the corrected data back to the RAM before it is transferred to the host system. The error correcting system includes an error syndrome generator and a error location and error value generator. In a first embodiment, the data codewords, comprised of user data and redundancy symbols, are stored from the recording device into the RAM. The error syndrome generator reads the codewords from the RAM, generates error syndromes, and transfers the error syndromes to the error location and error value generator. In an alternative embodiment, the error syndrome generator receives the codewords directly from the recording device.

Abstract: A rate 5/7, d=0 channel code encodes a Gray code servo track address into channel data recorded on a magnetic disk; a PR4 sliding threshold Viterbi sequence detector detects the recorded servo track address upon read back; a cost effective d=0 decoder decodes the recorded servo track address into its Gray code representation; and a 1/1+D filter decodes the Gray code track address into its binary representation. Detecting the servo data with a PR4 Viterbi sequence detector, which is already provided in a read channel for detecting user data, increases the data density of the storage system. The cost and complexity of the decoder is reduced by encoding/decoding the Gray code track address in sections of five bits.

Abstract: A sampled amplitude read channel reads data from a magnetic medium by detecting digital data from a sequence of discrete time sample values generated by sampling an analog read signal from a read head positioned over the magnetic medium. The digital data comprises a preamble field followed by a sync mark followed by a data field. Timing recovery in the read channel synchronizes to a phase and frequency of the preamble field and a sync detector detects the sync mark in order to frame operation of an RLL decoder for decoding the detected data field. To decrease the probability of early misdetection, the sync mark is chosen to have minimum correlation with shifted versions of the sync mark concatenated with the preamble field. To further increase the fault tolerance, the sync mark detector is enabled by timing recovery relative to the end of the preamble field.

Abstract: An error correction system (20) operates on clock cycles to decode a sequence of error correcting symbols (R(x)) received from a disk drive (24), and alternatively to encode data in a codeword for storage on a disk drive. The system includes a generator (30) which, during decoding, receives symbols of the sequence during a plurality of reception clock cycles. During the reception clock cycles the generator generates error pattern bits, regenerated CRC values, syndromes, and parity values. Also during the reception clock cycles the generator uses the regenerated CRC values and CRC symbols of the sequence to generate CRC check values. An error address determinator (90) uses the syndromes and parity values to determine, during a last of the reception clock cycles, a reference address (L) of an error burst in a data symbol portion of the sequence. An error pattern generator (80) then efficiently inserts the error pattern bits at the reference address in an output error pattern during a very next clock cycle.

Abstract: A one stage CRC generation system (400) and a two stage CRC generation system (600) feature a CRC generator/checker (700) which outputs a programmable number of CRC bytes. The CRC generation/checker (700) comprises a segmenting circuit (710) ?for segmenting an input stream of user data into a plurality m of sub-streams!; a circuit (712) which forms a linear combination of the plurality m of sub-streams and operates upon the linear combination in order to generate CRC bytes; and, a checker circuit (714) for comparing the generated CRC bytes with previously generated CRC bytes. The two stage system (600) includes a first CRC generator/checker (601); a memory (602) which receives both the user data and K.sub.1 number of primary CRC bytes generated by first CRC generator/checker (601); and, a second CRC generator/checker (603) which uses the primary CRC bytes and K.sub.1 number of its own generated verification CRC bytes to check the user data after retrieval from memory (602) and prior to encoding.

Abstract: A rate 16/17 ENDEC is disclosed which encodes 16 bit input data words into 17 bit codewords according to at least one predetermined code constraint, such as an RLL (d,k) constraint. The encoder encodes the high and low byte of the input data word using the same mapping circuitry which reduces its cost and complexity. The codewords are transferred through a communication channel, such as a computer disc storage device, and upon reception (or readback) the first 8 bits of the 17 bit codeword are decoded independent from the last 8 bits which prevents error propagation. That is, the first 8 bits of the codeword are decoded into a high byte of the decoded data word, and the last 8 bits of the codeword are decoded into a low byte of the decoded data word independent from one another.

Abstract: In a disc drive storage system employing a track level redundancy sector for reconstructing a data sector unrecoverable at the sector level, the latency of the storage system is minimized by performing a write operation according to the following steps:1. seek to the target track corresponding to the sector(s) to be written;2. once at the target track, wait for the recording head to reach the first sector in the track (sector 0);3. begin reading and processing the sectors in the target track to regenerate the redundancy sector;4. when the recording head reaches the target sector(s), combine the new data sector(s) with the regenerated redundancy sector, switch to a write operation, and write the new sectors to the track;5. after writing the new data sectors to the track, switch back to a read operation and continue reading the data sectors in the track and combining them with the regenerated redundancy sector; and6.

Abstract: In a magnetic disk drive storage system comprising a sampled amplitude read channel and an on-the-fly error correction coding (ECC) system, a thermal asperity compensation technique wherein: a thermal asperity (TA) detection circuit detects a saturation condition in the sample values of the analog read signal which indicates the presence of a TA; a pole of an AC coupling capacitor is elevated; timing recovery, gain control, and DC offset loops in the read channel are held constant; TA erasure pointers are generated corresponding to the duration of the TA transient; and an on-the-fly error detection and correction (EDAC) circuit processes the TA erasure pointers to correct errors in the detected digital data caused by the TA. Using TA erasure pointers to compensate for the effect of thermal asperities minimizes the cost, complexity, and redundancy of the ECC. Further, soft errors in the prior art method of adjusting the headroom of the read channel ADC are avoided.

Abstract: A one stage CRC generation system (400) and a two stage CRC generation system (600) feature a CRC generator/checker (700) which outputs a programmable number of CRC bytes. The CRC generation/checker (700) comprises a segmenting circuit (710) ?for segmenting an input stream of user data into a plurality m of sub-streams!; a circuit (712) which forms a linear combination of the plurality m of sub-streams and operates upon the linear combination in order to generate CRC bytes; and, a checker circuit (714) for comparing the generated CRC bytes with previously generated CRC bytes. The two stage system (600) includes a first CRC generator/checker (601); a memory (602) which receives both the user data and K.sub.1 number of primary CRC bytes generated by first CRC generator/checker (601); and, a second CRC generator/checker (603) which uses the primary CRC bytes and K.sub.1 number of its own generated verification CRC bytes to check the user data after retrieval from memory (602) and prior to encoding.

Abstract: An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM.sub.0 -REM.sub.3. The check remainder bytes REM.sub.0 -REM.sub.3 are utilized to generates syndromes S.sub.1, S.sub.3 and a factor S.sub.B, the syndromes in turn being used to obtain either one or two error location positions (.alpha..sup.L1, .alpha..sup.L2). The mathematical calculation circuit (104) not only generates the syndromes S.sub.1, S.sub.3 and factor S.sub.B, as well as the error location positions (.alpha..sup.L1, .alpha..