Abstract: In an error correction method for rotating magnetic media, CRC check remainder bytes are generated by using input data from a read sector to obtain regenerated CRC bytes for the read sector, and adding the regenerated CRC bytes to incoming CRC bytes of the read sector. Error patterns for correcting errors in the read sector are generated. Both the CRC check remainder bytes and the error patterns are used for confirming that the error patterns accurately correct the errors in the read sector. The confirmation involves loading a predetermined number of the CRC check remainder bytes into a corresponding number of registers (1302). For each of a plurality of error patterns of the sector, the error pattern is added to the register (1302) having its CRC check remainder bytes affected by the error pattern. A determination is then made whether the contents of any of the registers (1302) indicates inaccurate correction of the errors.

Abstract: A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter provides the two programmable delays using only one delay line thereby reducing the size and cost of the circuit. Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput.

Abstract: An error correction system (1000) included in a utilization device (1002) operates upon a plurality of sectors (S) stored in a data buffer (1100) for performing write-from-host and read-from-device operations. Overlapping and asynchronous operational steps are performed with respect to the plurality of sectors, the operational steps including sector transfer into buffer, sector correction, and sector transfer out of buffer. The error correction system (1000) includes a plurality of subsystems which are supervised and sequenced by correction controller (1020). The subsystems include a CRC generation and checking subsystem (1030); an LBA subsystem (1040); an ECC/Syndrome Generator subsystem (1050); a header (ID) subsystem (1060); a correction subsystem (1070); and, a correction checker system (1075).

Abstract: An error correction apparatus and method corrects an error burst occurring in the header information of a sector stored on a rotating magnetic storage medium, particularly sector identifying information. The apparatus (1000) comprises both a header correction subsystem (1060) for performing error correction upon the header information and a data correction subsystem (1075) for performing error correction upon the user data information. The header correction subsystem (1060) comprises a header correction unit (1250) which receives the header information from the medium and which generates an error pattern over the header information. A header register (1252) receives and stores the header information from the medium. The error pattern and the header information stored in the header register are used to obtain corrected header information.

Abstract: EDC/CRC checker (70) performs an EDC/CRC check as a block of data is being corrected during a correction pass, thereby obviating buffer access for EDC/CRC purposes subsequent to block correction. During the correction pass, an EDC/CRC sum is accumulated which, upon completion of the pass of the block, is zero if EDC/CRC bytes in the block confirm that the block has been corrected. During the single correction pass of the block, bytes of an uncorrected, most-recent codeword are added to the accumulated sum. Bytes of a previous codeword which have a byte synchronization relationship with the byte of the most-recent codeword are corrected (if necessary), and (when correction occurs) error pattern factors including error patterns used to correct the bytes of the previous codeword are also added to the accumulated sum.

Abstract: An error correction system operates in two modes: (1) a two-phased mode for correcting computer data having pointers; and (2) a subcode mode for correcting subcode packs included with audio digital data. During a first (two-phased) mode for correcting computer data with pointers, a generator (20), calculator (30), and corrector (60) are each operated during two phases. During a first phase (PTR.sub.-- TIME) the generator (20) generates one or two multi-bit buffer-obtained pointers (.alpha..sup.L0 =P.sub.0, .alpha..sup.L1 =P.sub.1) for the most-recent codeword while the calculator (30) uses syndromes (S.sub.0, S.sub.1) generated by generator (20) for a previous codeword CW.sub.n-1 to generate one or two error patterns (E.sub.0, E.sub.1) for the previous codeword. During a second phase (DATA.sub.-- TIME), the generator (20) generates syndromes (S.sub.0, S.sub.1) for the most-recent codeword CW.sub.

Abstract: A method and apparatus for encoding, detecting and decoding data in a Partial Response (PR) class-IV magnetic recording storage system that does not require the conventional interleave constraint and therefore minimizes the path memory and latency of a sequence detector such as the Maximum Likelihood (ML) Viterbi detector. Rather than encoding an interleave constraint to ensure merging of path memories in the detector, the parity of the encoded codewords is utilized in selecting tile correct sequence out of the unmerged paths. The encoding technique encodes the data using two groups of codewords; the first group causes the path memories of the sequence detector to merge into one survivor sequence and the second group causes the path memories to merge into two survivor sequences different in only one bit and thus different in parity. The correct survivor sequence is thereby selected according to the parity of the codeword being detected.

Abstract: A bit-oriented error correction calculation circuit performs numerous mathematical operations including bit-oriented convolutions, inversions, multiplications, additions, and bi-directional basis conversions. The circuit includes three banks of registers (400,401,402) connected as a convolution circuit to produce a sequence of inner products with respect to the first bank of registers (400) and the second bank of registers (401). Each of the banks of registers (400,401) has a bank loading switch (440,441,442) connected to a serial input terminal thereof for loading a selected one of a plurality of serial multibit values into the banks, including selective gating of feedback signals from respective feedback circuits (450,452) in registers (400,402) and (inter alia) constant values. The values of the feedback multipliers are selectively changeable in accordance with a field length of the value involved in error correction of data.

Abstract: A method and apparatus for encoding, detecting and decoding data in a Partial Response (PR) class-IV magnetic recording storage system that does not require the conventional interleave constraint and therefore minimizes the path memory and latency of a sequence detector such as the Maximum Likelihood (ML) Viterbi detector. Rather than encoding an interleave constraint to ensure merging of path memories, in the detector, the parity of the encoded codewords is utilized in selecting the correct sequence out of the unmerged paths. The encoding technique encodes the data using two groups of codewords: the first group causes the path memories of the sequence detector to merge into one survivor sequence, and the second group causes the path memories to merge into two survivor sequences different in only one bit and thus different in parity. The correct survivor sequence is thereby selected according to the parity of the codeword being detected.

Abstract: A burst error correction system comprising a CRC generator/checker; a syndrome/ECC generator; and an error corrector. Using codeword data, the CRC generator/checker generates m number of CRC bytes. The CRC bytes are shifted out to the syndrome/ECC generator for use in the generation of a plurality of ECC bytes. In a write operation, syndrome/ECC generator groups the data bytes and the CRC bytes for each codeword into a predetermined number of interleaves. The ECC bytes are generated so that the sum of the bytes in each interleave for a codeword is zero, and so that the ECC bytes generated by the syndrome/ECC generator constitute at least L number of consecutive roots of the codeword. The syndrome/ECC generator comprises an interleave dependent ECC factor subgenerator and two interleave independent ECC factor subgenerators.

Abstract: An apparatus and method of generating redundancy symbols and syndromes which is order-programmable is disclosed. The apparatus and method involves the implementation of an error correcting encoder/decoder for polynomial codes which uses a single circuit to generate check symbols during the transmit operation and to generate syndromes during a receive operation. The selection of roots for the code generator, and hence, the code order is programmable.

Abstract: An inversion circuit (212) determines an inverse B.sup.-1 of an m-bit symbol B, the symbol B being expressed in a dual basis representation. Inversion circuit (212) includes an iterative convolution circuit (124A, 124B, 124C) to which the symbol B is applied and which generates and stores electrical signals corresponding to an m-bit value A. The value A is in a first basis representation and is generated by the convolution circuit such that an inner product of A and .alpha..sup.k B is equal to 0 for k<m-1. A feedback circuit (128) is provided for enabling the convolution circuit to perform a convolution with an .alpha. multiple of B. A multiplier circuit (102) is connected to the convolution circuit and generates electrical output signals corresponding to the product of the value A and .alpha..sup.-t. The electrical output signals from the multiplier represent A.alpha..sup.-t =B.sup.-1 (i.e., the inverse of the m-bit symbol B in the first basis representation).

Abstract: Disclosed is a dual-purpose CRC generator which generates up to k CRC characters which can be used to extend the minimum distance of a three-way interleaved Reed-Solomon code by k and can also detect k random bit errors.

Abstract: A Reed-Solomon decoder (199) processes a codeword containing n m-bit symbols to determine coefficients of an error locator polynomial .sigma.(x), and thereafter generates an error evaluator polynomial .omega.(x). The decoder comprises a bank (B103) of syndrome registers (103) for storing syndrome values; a bank (B101) of error locator registers (101) for accumulating therein coefficients of an error locator polynomial .sigma.(x); and, a bank (B102) of intermediate registers (102) for accumulating therein coefficients of an intermediate polynomial .tau.(x). The decoder (199) further includes a register update circuit (50) which, for a given codeword, conducts two-phased error locator iterations in order to update values in the error locator registers and the intermediate registers. In contrast to prior art techniques, the register update circuit (50) of the present invention updates coefficients of the intermediate polynomial .tau.

Abstract: The error correction apparatus of this invention maintains a set of pointers which are used to supplement the error correction characters written into the data tracks of the data frame. These pointers consist of indicators stored in a memory that note the location and nature of errors detected in the present data frame or in previous data frames read from the magnetic tape and stored in a buffer memory. The pointer information can be used by the error correction circuitry to determine which tracks typically produce the errors in the data frame. The error correction circuitry can then generate error patterns which can be combined with the data read and reread from the buffer to correct the errors contained therein.

Abstract: A dual channel helical scan recording system (30) includes a rotating dum (36) having sets of heads (W1, W2) (R1, R2) mounted on its peripheral surface (56). A set of write heads (W1, W2) is situated on an opposite side of the drum (36) from a set of read heads (R1, R2). The write heads (W1, W2) simultaneously write two adjaent tracks (T1, T2), which are read for verification 180 detrees later by corresponding read heads (R1, R2). The heads (W1, W2, R1, R2) are strategically mounted on the drum (36) with respect to angular and axial placement, and have selected head widths and azimuthal angles. Should a block of data (317) written to tape (32) be determined, during readback, to be bad block, that bad block is subsequently rewritten on the tape (32) in the course of writing good blocks and amongst other good blocks. The rewritten block is recorded at a row position on the tape which is sufficiently displaced from the row position of a previous writing to avoid media defects occuring on the tape.

Abstract: In a method of encoding and decoding informational data for transmission to a storage medium, a group G of physical blocks written to the storage medium includes both user data information blocks and auxiliary error correction blocks. Each block (B.sub.r,c) included in the group G belongs both to a row r and a column c. Informational data is formatted into preselected bit positions of the user data information blocks. Values for bit positions in the auxiliary error correction blocks are generated by performing an exclusive OR operation upon values in corresponding bit positions in a subgroup of strategically selected user data blocks. By strategically selecting the user data blocks to be included in the subgroup, the method facilitates recovery of entire blocks, and even rows or columns of blocks.

Abstract: For decoding a Reed-Solomon codeword with (n-K) check characters an error/erasure locator (32) executes a codeword cycle comprising (n-K) "coefficient" iterations followed by (n-K) "modified syndrome" iterations. The error/erasure locator (32) includes a bank (52) of simultaneously loadable syndrome registers and a bank (56) of coefficient registers. The syndrome registers are connected to one another in a circular shift path (91). The error/erasure locator (32) further includes a cascading arrangement of PISO multipliers (54), a SIPO multiplier (60), and PISO multipliers (61). The PISO multipliers (54) operate upon the contents of the syndrome registers (52) (expressed in a conventional basis representation) and the contents of the coefficient register (56) (expressed in dual basis representation) to obtain a serial current discrepancy d.sub.n. The SIPO multiplier 60 multiplies the serial current discrepancy d.sub.n by a parallel-formatted multiplicative inverse d.sub.m.sup.-1 .beta..sub.

Abstract: An error correction system (20) comprises a multi-pass controller (32) which operates through a controller/decoder interface (34) to supervise the execution of decoding passes by a decoder (30). The multi-pass controller (32) employs a correction procedure comprising a plurality of hierarchial strategies S(1), S(2), . . . S(N) for transitioning the procedure through a plurality of predetermined states. Upon completion of a decoding pass, a pass evaluator (70) evaluates the results of the decoding pass and uses the evaluation for establishing values for further operation. Further passes are executed in accordance with further states determined by the multi-pass controller (32), the further states having particular parameters associated therewith including a strategy selection.

Abstract: Apparatus and method are disclosed for formatting and recording digital information. Recording is effected by discrete stripes on 8 mm magnetic tape using a helical scan arrangement that enables a high recording density and a low error rate. Formatting in the data area of each stripe includes recording of digital information within preamble, data block, and postamble sections. The preamble section provides frequency/phase and location referencing, the data block section includes a plurality of physical data blocks each of which are divided into sub-blocks that include synchronizing and identifying information along with data to be recorded, and the postamble section ensures compatibility of physical alignment between the recording heads and magnetic tape.