Abstract: An imaging system may include an array of image sensor pixels, each image sensor pixel including a photosensitive element coupled to time trace generation circuitry having a first CCD register. The time trace generation circuitry may be coupled to integration circuitry having a second integration CCD register via corresponding charge transfer structures. The second integration CCD register may integrate multiples sets of sampled charge from the first CCD register to improve the signal-to-noise ratio of the collected time trace information. The time trace generations circuitry or integration circuitry may also include background light subtract capabilities to remove background light level from the collected time trace information.

Abstract: A global shutter image sensor may include a charge coupled device to store charge while mitigating dark current. The image sensor may include a first semiconductor substrate with a photodiode, a floating diffusion region, a transfer transistor coupled between the photodiode and the floating diffusion region, and a source follower transistor having a gate coupled to the floating diffusion region. The image sensor may include a second semiconductor substrate with an analog memory charge coupled device. The charge coupled device may include an input gate that is coupled to the source follower transistor in the first substrate, a charge injector, at least one storage gate, and an output gate. The charge coupled device may store samples correlated to charge on the floating diffusion region in the first substrate. During readout, the samples may sequentially be transferred to an additional floating diffusion region in the second substrate using the output gate.

Abstract: An imaging device may include one or more photosensitive regions in a pixel formed as part of an image pixel array. Microlenses and color filter structures may be formed over the pixel. Each microlens may be formed from a microlens seed and one or more deposition microlens layers formed over the microlens seed. The deposition microlens layer(s) as deposited may already define the curvature of the microlens. As such, no further etching or smoothing process is need for the microlens layer(s) formed over the microlens seed. If desired, the microlens seed may have a planar top surface and planar sides, a planar top surface and slanted planar sides, or a nonplanar top surface and planar sides. The microlens seed may define microlens characteristics of the microlens such as the radius of curvature, the height, and/or the number and type of microlens lobes.

Abstract: An image sensor may include imaging pixels with non-destructive readout capabilities. Each imaging pixel may include a substrate having a photosensitive area that generates charge in response to incident light. The charge may accumulate at a front side of the substrate adjacent to a floating gate. The voltage of the floating gate may depend on how much charge is accumulated. The voltage of the floating gate may be repeatedly sampled to monitor the amount of incident light received over time. A first reset transistor may clear the substrate of accumulated charge. A second reset transistor may reset the voltage of the floating gate. The imaging pixel may be split between multiple wafers if desired and may include nMOS and pMOS transistors.

Abstract: A time delay integration image sensor may include a number of charge coupled devices (CCDs) that transfer charge in synchronization with the movement of an object being imaged. To increase the dynamic range of the image sensor, the image sensor may include circuitry configured to non-destructively sample the charge as it is transferred through the charge coupled devices. Floating gates may be included in the image sensor and may have a voltage that is proportional to the charge accumulated under the floating gates. Each floating gate may be coupled to a respective readout circuit in an additional substrate by a metal interconnect layer.

Abstract: A time delay integration image sensor may include a number of charge coupled devices (CCDs) that transfer charge in synchronization with the movement of an object being imaged. To increase the dynamic range of the image sensor, the image sensor may include circuitry configured to non-destructively sample the charge as it is transferred through the charge coupled devices. Floating gates may be included in the image sensor and may have a voltage that is proportional to the charge accumulated under the floating gates. Each floating gate may be coupled to a respective readout circuit in an additional substrate by a metal interconnect layer.

Abstract: An image sensor may include imaging pixels with non-destructive readout capabilities. Each imaging pixel may include a substrate having a photosensitive area that generates charge in response to incident light. The charge may accumulate at a front side of the substrate adjacent to a floating gate. The voltage of the floating gate may depend on how much charge is accumulated. The voltage of the floating gate may be repeatedly sampled to monitor the amount of incident light received over time. A first reset transistor may clear the substrate of accumulated charge. A second reset transistor may reset the voltage of the floating gate. The imaging pixel may be split between multiple wafers if desired and may include nMOS and pMOS transistors.

Abstract: A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include multiple output stages, each of which can include a source-follower transistor coupled in series with a current sink transistor and at least one cascode transistor. The current sink transistor may have its gate terminal shorted to ground. In one arrangement, the cascode transistor has a gate terminal that receives a non-zero bias voltage. In another arrangement, the cascode transistor has a gate terminal that is also shorted to ground and operates in depletion mode.

Abstract: A method of binning charges in a charge coupled device (CCD) image sensor is described. The frequency at which an HCCD in the CCD image sensor is clocked may be a multiple of the frequency at which a summing element coupled to the end of the HCCD is clocked, such that charges may be binned at a gate within the HCCD or at the summing element before being read out. The clock signal for the summing element may have a 50% duty cycle in order to provide additional time for charge to flow across an output gate to a floating diffusion node in an output stage of the CCD image sensor. For cases where the HCCD clock frequency is more than twice the summing element clock frequency, charges may be binned at the summing element. Otherwise, charges may be binned at another gate within the HCCD.

Abstract: A method of forming a microlens may include using two layers of photoresist. The first photoresist layer may be patterned to form a first portion of a pixel microlens. A second photoresist layer may be patterned on top of the first portion of the pixel microlens. The second photoresist may then be melted so that the second photoresist layer has a curved upper surface. The first and second photoresist layers may combine to form the pixel microlens. The indices of refraction of the first and second photoresist layers may the same or different. The melting point of the second photoresist may be lower than the melting point of the first photoresist.

Abstract: The present invention relates to novel canine distemper virus (CDV) neutralization-resistant mutants, methods for making the same and uses for vaccine production.

Abstract: Methods of measuring and calibrating the gain of a CCD imaging system are described. Charge injectors may be present on either side of an image sensor array that provide test charges to respective calibration VCCDs. Test charges may be transferred to upper and lower HCCDs during quad-output read out or to only the lower HCCD during dual-output or single-output read out. In each quadrant of the imaging system, test charges may be transferred to an EMCCD output or to a non-EMCCD output via a charge switch based on the magnitude of the test charges. The gains of all EMCCD outputs and non-EMCCD outputs in the imaging system may be calibrated against one another by adjusting the gain at each output when a discrepancy is detected between any two outputs.

Abstract: In electron multiplying charge coupled device (EMCCD) image sensors, electron traps in the dielectric stack underneath charge multiplication electrodes may cause undesirable gain ageing. To reduce the gain ageing drift effect, a dielectric stack may be formed that does not include electron traps in regions underneath charge multiplication electrodes. To accomplish this, silicon nitride in the dielectric stack may be removed in regions underneath the charge multiplication electrodes. The EMCCD image sensors can thus be fabricated with a stable charge carrier multiplication gain during their operational lifetime.

Abstract: A method of forming a microlens may include using two layers of photoresist. The first photoresist layer may be patterned to form a first portion of a pixel microlens. A second photoresist layer may be patterned on top of the first portion of the pixel microlens. The second photoresist may then be melted so that the second photoresist layer has a curved upper surface. The first and second photoresist layers may combine to form the pixel microlens. The indices of refraction of the first and second photoresist layers may the same or different. The melting point of the second photoresist may be lower than the melting point of the first photoresist.

Abstract: Methods of measuring and calibrating the gain of a CCD imaging system are described. Charge injectors may be present on either side of an image sensor array that provide test charges to respective calibration VCCDs. Test charges may be transferred to upper and lower HCCDs during quad-output read out or to only the lower HCCD during dual-output or single-output read out. In each quadrant of the imaging system, test charges may be transferred to an EMCCD output or to a non-EMCCD output via a charge switch based on the magnitude of the test charges. The gains of all EMCCD outputs and non-EMCCD outputs in the imaging system may be calibrated against one another by adjusting the gain at each output when a discrepancy is detected between any two outputs.

Abstract: A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include multiple output stages, each of which can include a source-follower transistor coupled in series with a current sink transistor and at least one cascode transistor. The current sink transistor may have its gate terminal shorted to ground. In one arrangement, the cascode transistor has a gate terminal that receives a non-zero bias voltage. In another arrangement, the cascode transistor has a gate terminal that is also shorted to ground and operates in depletion mode.

Abstract: A method of binning charges in a charge coupled device (CCD) image sensor is described. The frequency at which an HCCD in the CCD image sensor is clocked may be a multiple of the frequency at which a summing element coupled to the end of the HCCD is clocked, such that charges may be binned at a gate within the HCCD or at the summing element before being read out. The clock signal for the summing element may have a 50% duty cycle in order to provide additional time for charge to flow across an output gate to a floating diffusion node in an output stage of the CCD image sensor. For cases where the HCCD clock frequency is more than twice the summing element clock frequency, charges may be binned at the summing element. Otherwise, charges may be binned at another gate within the HCCD.

Abstract: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

Abstract: The present invention relates to novel canine distemper virus (CDV) neutralization-resistant mutants, methods for making the same and uses for vaccine production.

Abstract: An image sensor and method for measuring a refractive index of a material includes a semiconductor substrate having an exposed surface for facing the material, an array of pixels on the semiconductor substrate spaced from the exposed surface, and a light source on the semiconductor substrate configured to emit light into the semiconductor substrate toward the exposed surface to reflect the light off the exposed surface toward the array of pixels, wherein the array of pixels detect the light reflected by the exposed surface for calculating the refractive index of the material.