Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes instructing a communication fabric to establish a first logical partition in the communication fabric that includes a first processing device and a memory device, and directing transfer of configuration data for storage by the memory device over the first logical partition. After transfer of the configuration data, the method includes instructing the communication fabric to remove the first logical partition in the communication fabric, where the configuration data remains stored by the memory device after removal of the first logical partition. The method also includes instructing the communication fabric to establish a second logical partition in the communication fabric that includes at least a second processing device and the memory device comprising the configuration data, where the second processing device is operated using the configuration data.

Abstract: A data storage card insertable into a peripheral slot of host system is provided that houses storage devices on both sides of the data storage card. A heat sink member establishes a skewed offset stackup among a primary circuit board and a secondary circuit board, and a circuit interconnect element couples across the skewed offset stackup between the circuit boards. The primary circuit board comprises an edge connector insertable into a peripheral slot connector and is configured to carry host signaling for the computer peripheral device. The secondary circuit board comprises a first set of data storage device connectors on a first side and a second set of data storage connectors on a second side. The skewed offset stackup allows for a thickness of storage devices inserted on both the first side and the second side to fit within a slot width of the peripheral slot.

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a management processor configured to initiate a communication arrangement between a first endpoint device coupled to a communication fabric and a second endpoint device coupled to the communication fabric. The communication arrangement is configured to redirect a transfer from the first endpoint device based on an address corresponding to an address range of the second endpoint device without passing the transfer through a host processor coupled to the communication fabric that executes an application initiating the transfer.

Abstract: Communication fabric-coupled computing architectures, platforms, and systems are provided herein. In one example, an apparatus includes a management entity configured to establish a compute unit comprising components from among a plurality of physical computing components by at least instructing a communication fabric communicatively coupling the plurality of physical computing components to establish logical isolation within the communication fabric to form the compute unit. Responsive to an indication of a change in workload associated with at least a software component deployed to a processing element of the compute unit, the management entity is configured to adjust the logical isolation to alter a quantity of the plurality of physical computing components in the compute unit in accordance with the change in the workload.

Abstract: Systems, methods, apparatuses, and software for computing systems are provided herein. In one example, a system includes a processor configured to communicate over a network interface and a processor peripheral communication interface. The system includes communication switch circuitry communicatively coupling the processor peripheral communication interface and a device peripheral communication interface of an endpoint device. The communication switch circuitry is configured to establish logical isolation among ports of the communication switch circuitry by instantiating visibility over the logical isolation among the processor and the endpoint device. The processor is configured to determine transactions received over the network interface are targeted for the endpoint device, and transfer at least data of the transactions over the communication switch circuitry for receipt by the endpoint device.

Abstract: Emulated telemetry interfaces for host processors and management processors coupled over communication fabrics are presented herein. In one example, an apparatus includes a monitoring function executed by a host processor configured to determine telemetry related to operation of at least the host processor. A driver function executed by the host processor is configured to emulate operation of a network interface to an operating system of the host processor for transfer of communications comprising at least the telemetry to a management processor over a communication fabric different than the network interface, where the host processor and the management processor are communicatively coupled to the communication fabric.

Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.

Abstract: Designs for enabling safe insertion and removal of computing components from a live motherboard are presented herein. In one example, a method includes maintaining a slot power connection and an auxiliary power connection for a peripheral card slot in a powered-off state, and sensing insertion of a peripheral card into the peripheral card slot and responsively detecting whether the auxiliary power connection is employed by the peripheral card. Based on detecting the auxiliary power connection is employed by the peripheral card, the method further includes applying current limits selected for the peripheral card to the slot power connection and the auxiliary power connection and concurrently enabling the slot power connection and the auxiliary power connection for the peripheral card.

Abstract: Peer-to-peer arrangements between endpoint devices are provided herein. A method includes establishing synthetic devices representing endpoint devices in an address domain associated with a host processor, where the endpoint devices have a different address domain than the host processor. The method also includes forming a peer arrangement between the endpoint devices such that data transfers between the endpoint devices in the different address domain can be initiated by the host processor interfacing with the synthetic devices.

Abstract: Peer-to-peer arrangements between graphics processing units (GPUs) are provided herein. A method includes establishing synthetic devices representing GPUs in an address domain associated with a host processor, where the GPUs have a different address domain than the host processor. The method also includes forming a peer arrangement between the GPUs such that data transfers between the GPUs in the different address domain can be initiated by the host processor interfacing with the synthetic devices.

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.

Abstract: Deployment of arrangements of physical computing components coupled over a communication fabric are presented herein. In one example, a method includes coupling into a communication fabric a plurality of communication interfaces provided by a baseboard hosting a plurality data processing devices. The method includes establishing a one-hop latency in the communication fabric between the plurality of data processing devices and peripheral card slots, and establishing a two-hop latency in the communication fabric between the plurality of data processing devices and additional peripheral card slots. The method also includes establishing interconnect pathways between a plurality of communication switches that provide the one-hop latency through one or more cross-connect communication switches that provide the two-hop latency.

Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.

Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.

Abstract: A method of programming a fabric-coupled FPGA device includes instructing a communication fabric to establish a first logical partition segregating a first set of communication switch ports within the communication fabric that includes the management processor and a target device comprising a memory device configured to program a field-programmable gate array (FPGA). The method includes directing configuration data configured to program the FPGA to the target device over the first logical partition. The method includes instructing the communication fabric to remove the first logical partition in the communication fabric, wherein the configuration data remains stored at the target device after removal of the first logical partition. The method includes instructing the communication fabric to establish a second logical partition segregating a second set of communication switch ports within the communication fabric that includes a selected device and the target device that stores the configuration data.

Abstract: Deployment of arrangements of physical computing components coupled over a communication fabric are presented herein. In one example, a method includes coupling into a communication fabric a plurality of communication interfaces provided by a baseboard hosting a plurality data processing devices. The method includes establishing a one-hop latency in the communication fabric between the plurality of data processing devices and peripheral card slots, and establishing a two-hop latency in the communication fabric between the plurality of data processing devices and additional peripheral card slots. The method also includes establishing interconnect pathways between a plurality of communication switches that provide the one-hop latency through one or more cross-connect communication switches that provide the two-hop latency.

Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.

Abstract: Designs for enabling safe insertion and removal of computing components from a live motherboard are presented herein. In one example, a method includes maintaining a slot power connection and an auxiliary power connection for a peripheral card slot in a powered-off state, and sensing insertion of a peripheral card into the peripheral card slot and responsively detecting whether the auxiliary power connection is employed by the peripheral card. Based on detecting the auxiliary power connection is employed by the peripheral card, the method further includes applying current limits selected for the peripheral card to the slot power connection and the auxiliary power connection and concurrently enabling the slot power connection and the auxiliary power connection for the peripheral card.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes instructing a PCIe fabric communicatively coupling a plurality of physical computing components including PCIe devices and one or more PCIe switches to establish a first PCIe communication path between the management processor and a target PCIe device. The method also includes directing at least configuration data to the target PCIe device using the first PCIe communication path and instructing the PCIe fabric to remove the first PCIe communication path between the management processor and the target PCIe device. The method also includes instructing the PCIe fabric to establish a second PCIe communication path between a selected PCIe device and the target PCIe device configured according to the configuration data.

Abstract: Emulated telemetry interfaces for host processors and management processors coupled over communication fabrics are presented herein. In one example, an apparatus includes a monitoring function executed by a host processor configured to determine telemetry related to operation of at least the host processor. A driver function executed by the host processor is configured to emulate operation of a network interface to an operating system of the host processor for transfer of communications comprising at least the telemetry to a management processor over a communication fabric different than the network interface, where the host processor and the management processor are communicatively coupled to the communication fabric.