Patents by Inventor Christopher R. Long

Christopher R. Long has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230016542
    Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventors: Christopher R. Long, Andrew Rudolph Heyd, Brenden Rust
  • Patent number: 11531629
    Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: December 20, 2022
    Assignee: Liqid Inc.
    Inventors: Christopher R. Long, Andrew Rudolph Heyd, Brenden Rust
  • Publication number: 20220318181
    Abstract: A method of programming a fabric-coupled FPGA device includes instructing a communication fabric to establish a first logical partition segregating a first set of communication switch ports within the communication fabric that includes the management processor and a target device comprising a memory device configured to program a field-programmable gate array (FPGA). The method includes directing configuration data configured to program the FPGA to the target device over the first logical partition. The method includes instructing the communication fabric to remove the first logical partition in the communication fabric, wherein the configuration data remains stored at the target device after removal of the first logical partition. The method includes instructing the communication fabric to establish a second logical partition segregating a second set of communication switch ports within the communication fabric that includes a selected device and the target device that stores the configuration data.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 6, 2022
    Inventors: James Scott Cannata, Christopher R. Long, Phillip Clark, Sumit Puri
  • Publication number: 20220283960
    Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.
    Type: Application
    Filed: October 20, 2021
    Publication date: September 8, 2022
    Inventors: Christopher R. Long, Andrew Rudolph Heyd, Brenden Russ
  • Publication number: 20220283976
    Abstract: Designs for enabling safe insertion and removal of computing components from a live motherboard are presented herein. In one example, a method includes maintaining a slot power connection and an auxiliary power connection for a peripheral card slot in a powered-off state, and sensing insertion of a peripheral card into the peripheral card slot and responsively detecting whether the auxiliary power connection is employed by the peripheral card. Based on detecting the auxiliary power connection is employed by the peripheral card, the method further includes applying current limits selected for the peripheral card to the slot power connection and the auxiliary power connection and concurrently enabling the slot power connection and the auxiliary power connection for the peripheral card.
    Type: Application
    Filed: November 11, 2021
    Publication date: September 8, 2022
    Inventor: Christopher R. Long
  • Publication number: 20220283974
    Abstract: Deployment of arrangements of physical computing components coupled over a communication fabric are presented herein. In one example, a method includes coupling into a communication fabric a plurality of communication interfaces provided by a baseboard hosting a plurality data processing devices. The method includes establishing a one-hop latency in the communication fabric between the plurality of data processing devices and peripheral card slots, and establishing a two-hop latency in the communication fabric between the plurality of data processing devices and additional peripheral card slots. The method also includes establishing interconnect pathways between a plurality of communication switches that provide the one-hop latency through one or more cross-connect communication switches that provide the two-hop latency.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 8, 2022
    Applicant: Liqid Inc.
    Inventor: Christopher R. Long
  • Patent number: 11392525
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes instructing a PCIe fabric communicatively coupling a plurality of physical computing components including PCIe devices and one or more PCIe switches to establish a first PCIe communication path between the management processor and a target PCIe device. The method also includes directing at least configuration data to the target PCIe device using the first PCIe communication path and instructing the PCIe fabric to remove the first PCIe communication path between the management processor and the target PCIe device. The method also includes instructing the PCIe fabric to establish a second PCIe communication path between a selected PCIe device and the target PCIe device configured according to the configuration data.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 19, 2022
    Assignee: Liqid Inc.
    Inventors: James Scott Cannata, Christopher R. Long, Phillip Clark, Sumit Puri
  • Publication number: 20220214987
    Abstract: Peer-to-peer arrangements between graphics processing units (GPUs) are provided herein. A method includes establishing synthetic devices representing GPUs in an address domain associated with a host processor, where the GPUs have a different address domain than the host processor. The method also includes forming a peer arrangement between the GPUs such that data transfers between the GPUs in the different address domain can be initiated by the host processor interfacing with the synthetic devices.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: James Scott Cannata, German Kazakov, Christopher R. Long, Jason Breakstone
  • Publication number: 20220214989
    Abstract: Emulated telemetry interfaces for host processors and management processors coupled over communication fabrics are presented herein. In one example, an apparatus includes a monitoring function executed by a host processor configured to determine telemetry related to operation of at least the host processor. A driver function executed by the host processor is configured to emulate operation of a network interface to an operating system of the host processor for transfer of communications comprising at least the telemetry to a management processor over a communication fabric different than the network interface, where the host processor and the management processor are communicatively coupled to the communication fabric.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Inventors: James Scott Cannata, Christopher R. Long, Jason Breakstone
  • Publication number: 20220206687
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes instructing a communication fabric to establish a first logical partition in the communication fabric that includes a first processing device and a memory device, and directing transfer of configuration data for storage by the memory device over the first logical partition. After transfer of the configuration data, the method includes instructing the communication fabric to remove the first logical partition in the communication fabric, where the configuration data remains stored by the memory device after removal of the first logical partition. The method also includes instructing the communication fabric to establish a second logical partition in the communication fabric that includes at least a second processing device and the memory device comprising the configuration data, where the second processing device is operated using the configuration data.
    Type: Application
    Filed: January 13, 2022
    Publication date: June 30, 2022
    Applicant: Liqid Inc.
    Inventors: James Scott Cannata, Christopher R. Long, Phillip Clark, Sumit Puri
  • Patent number: 11314677
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes receiving user input to establish a compute unit comprising a host processor and at least two graphics processing units (GPUs) having a peer-to-peer capability. The method also includes instructing a management element for a communication fabric to form the compute unit and communicatively couple the host processor and the at least two GPUs over the communication fabric. The method also includes instructing the management element to establish an isolation function to form the peer arrangement between the at least two GPUs in the communication fabric, where the isolation function isolates a first address domain associated with the at least two GPUs from at least a second address domain associated with the host processor by at least establishing synthetic devices representing the at least two GPUs in the second address domain.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: April 26, 2022
    Assignee: Liqid Inc.
    Inventors: James Scott Cannata, German Kazakov, Christopher R. Long, Jason Breakstone
  • Patent number: 11294839
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating compute units is presented that includes forming compute units among a plurality of physical computing components coupled over a Peripheral Component Interconnect Express (PCIe) fabric configured to communicatively couple the plurality of physical computing components and isolate the compute unit using logical partitioning within the PCIe fabric. The method also includes initiating a software component deployed to at least associated CPUs within the compute units, reporting telemetry to the management processor related to operation of the compute unit, and emulating operation of at least one among an Ethernet and InfiniBand interface to an operating system of the associated CPU for transfer of communications comprising at least the telemetry to the management processor over the PCIe fabric.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: April 5, 2022
    Assignee: Liqid Inc.
    Inventors: Christopher R. Long, James Scott Cannata, Jason Breakstone
  • Publication number: 20220004512
    Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.
    Type: Application
    Filed: August 30, 2021
    Publication date: January 6, 2022
    Applicant: Liqid Inc.
    Inventors: James Scott Cannata, Christopher R. Long, Sumit Puri, Bryan Schramm
  • Patent number: 11119957
    Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 14, 2021
    Assignee: Liqid Inc.
    Inventors: James Scott Cannata, Christopher R. Long, Sumit Puri, Bryan Schramm
  • Publication number: 20210240538
    Abstract: Communication fabric-coupled computing architectures, platforms, and systems are provided herein. In one example, an apparatus includes a management entity configured to establish a compute unit comprising components from among a plurality of physical computing components by at least instructing a communication fabric communicatively coupling the plurality of physical computing components to establish logical isolation within the communication fabric to form the compute unit. Responsive to an indication of a change in workload associated with at least a software component deployed to a processing element of the compute unit, the management entity is configured to adjust the logical isolation to alter a quantity of the plurality of physical computing components in the compute unit in accordance with the change in the workload.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Applicant: Liqid Inc.
    Inventors: Christopher R. Long, James Scott Cannata, Jason Breakstone
  • Publication number: 20210191894
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes receiving user input to establish a compute unit comprising a host processor and at least two graphics processing units (GPUs) having a peer-to-peer capability. The method also includes instructing a management element for a communication fabric to form the compute unit and communicatively couple the host processor and the at least two GPUs over the communication fabric. The method also includes instructing the management element to establish an isolation function to form the peer arrangement between the at least two GPUs in the communication fabric, where the isolation function isolates a first address domain associated with the at least two GPUs from at least a second address domain associated with the host processor by at least establishing synthetic devices representing the at least two GPUs in the second address domain.
    Type: Application
    Filed: January 29, 2021
    Publication date: June 24, 2021
    Inventors: James Scott Cannata, German Kazakov, Christopher R. Long, Jason Breakstone
  • Patent number: 10993345
    Abstract: A storage card insertable into a host system is provided that includes a plurality of storage devices connectors. The storage card include slot offset features to offset a circuit board of the storage card from a host system slot alignment. This offset provides for storage device connector placement on both sides of the storage card. The storage card also can include a Peripheral Component Interconnect Express (PCIe) switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage card, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage card and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 27, 2021
    Assignee: Liqid Inc.
    Inventors: Bryan Schramm, Andrew Rudolph Heyd, Brenden Michael Rust, Christopher R. Long, Sumit Puri
  • Patent number: 10990553
    Abstract: Enhanced data storage devices in various form factors are discussed herein. In one example, a storage drive includes a 2.5-inch form factor chassis that structurally supports elements of the storage drive, and at least one host connector. The storage drive also includes a plurality of M.2 storage device connectors, and a Peripheral Component Interconnect Express (PCIe) switch circuit configured to receive storage operations over the at least one host connector and transfer the storage operations for delivery to ones of the plurality of M.2 storage device connectors over associated device PCIe interfaces. The storage drive also includes power circuitry configured to provide holdup power to ones of the plurality of M.2 storage device connectors after loss of input power over the at least one host connector.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: April 27, 2021
    Assignee: Liqid Inc.
    Inventors: Brenden Michael Rust, Christopher R. Long, Andrew Rudolph Heyd, Sumit Puri, Bryan Schramm, Seth Walsh, Jason Breakstone
  • Patent number: 10983941
    Abstract: Various computer peripheral cards, devices, systems, methods, and software are provided herein. In one example, a storage apparatus includes a plurality of storage device connectors in a stacked arrangement, each configured to mate with associated storage devices and carry Peripheral Component Interconnect Express (PCIe) signaling for the associated storage devices. The storage apparatus also includes a PCIe switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage apparatus, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage apparatus and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 20, 2021
    Assignee: Liqid Inc.
    Inventors: Andrew Rudolph Heyd, Christopher R. Long, James Scott Cannata, Jason Breakstone
  • Patent number: 10983834
    Abstract: Communication fabric-coupled computing architectures, platforms, and systems are provided herein. In one example, an apparatus includes a management entity configured to establish compute units each comprising components selected among a plurality of physical computing components. The apparatus includes a fabric interface configured to instruct a communication fabric communicatively coupling the plurality of physical computing components to establish logical isolation within the communication fabric to form the compute units.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 20, 2021
    Assignee: Liqid Inc.
    Inventors: Christopher R. Long, James Scott Cannata, Jason Breakstone