Abstract: Rackmount Peripheral Component Interconnect Express (PCIe) switch assemblies are provided herein. One example PCIe switch assembly includes an enclosure that encases elements of the PCIe switch assembly, a first plurality of PCIe interconnect ports positioned on a front side of the PCIe switch assembly, and a second plurality of PCIe interconnect ports positioned on a rear side of the PCIe switch assembly. One or more redundancy cross-link ports are provided to handle failover traffic with at least another PCIe switch assembly. PCIe switch circuitry is communicatively coupled to the first plurality of PCIe interconnect ports and the second plurality of PCIe interconnect ports that form a cluster interconnect PCIe fabric. A control processor is configured to control operation of at least the PCIe switch circuitry and the one or more redundancy cross-link ports.

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes instructing a PCIe fabric communicatively coupling a plurality of physical computing components including PCIe devices and one or more PCIe switches to establish a first PCIe communication path between the management processor and a target PCIe device. The method also includes directing at least configuration data to the target PCIe device using the first PCIe communication path and instructing the PCIe fabric to remove the first PCIe communication path between the management processor and the target PCIe device. The method also includes instructing the PCIe fabric to establish a second PCIe communication path between a selected PCIe device and the target PCIe device configured according to the configuration data.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes receiving user input to establish a compute unit comprising a host processor and at least two graphics processing units (GPUs) having a peer-to-peer capability. The method also includes instructing a management element for a communication fabric to form the compute unit and communicatively couple the host processor and the at least two GPUs over the communication fabric. The method also includes instructing the management element to establish an isolation function to form the peer arrangement between the at least two GPUs in the communication fabric, where the isolation function isolates a first address domain associated with the at least two GPUs from at least a second address domain associated with the host processor by at least establishing synthetic devices representing the at least two GPUs in the second address domain.

Abstract: Communication fabric-coupled computing architectures, platforms, and systems are provided herein. In one example, an apparatus includes a management entity configured to establish compute units each comprising components selected among a plurality of physical computing components. The apparatus includes a fabric interface configured to instruct a communication fabric communicatively coupling the plurality of physical computing components to establish logical isolation within the communication fabric to form the compute units.

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, a computing system is provided. The computing system includes a management processor configured to initiate a peripheral component interconnect express (PCIe) arrangement between a host processor and a plurality of PCIe devices over a PCIe fabric comprising one or more PCIe switches. The PCIe arrangement is established to detect a data transfer directed to an expanded address of a greater length than a destination field of the PCIe communications of the detected data transfer by using at least another portion of the PCIe communications to store a portion of the expanded address that is in excess of the length than the destination field of the PCIe communications, and route the detected data transfer over the PCIe fabric to a destination device associated with the expanded address.

Abstract: A storage card insertable into a host system is provided that includes a plurality of storage devices connectors. The storage card include slot offset features to offset a circuit board of the storage card from a host system slot alignment. This offset provides for storage device connector placement on both sides of the storage card. The storage card also can include a Peripheral Component Interconnect Express (PCIe) switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage card, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage card and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating compute units is presented that includes forming compute units among a plurality of physical computing components comprising at least central processing units (CPUs), storage modules, and network interface modules coupled over a Peripheral Component Interconnect Express (PCIe) fabric configured to communicatively couple the plurality of physical computing components and isolate the compute unit in the clustered environment using logical partitioning within the PCIe fabric. The method also includes initiating a software component deployed to at least associated CPUs within the compute units, reporting telemetry to the management processor related to operation of the compute unit, and emulating operation of an Ethernet interface to an operating system of the associated CPU for transfer of communications comprising at least the telemetry to the management processor over the PCIe fabric.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data system is provided. The method includes initiating an isolation function in a communication fabric to form a peer arrangement between graphics processing units (GPUs) coupled to the communication fabric. The isolation function isolates a first address domain associated with the GPUs from at least a second address domain associated with the host by at least establishing synthetic devices representing the GPUs in the second address domain.

Abstract: A connectivity card insertable into a connector of a host system is provided. The connectivity card includes a plurality of Peripheral Component Interconnect Express (PCIe) connectors configured to provide external PCIe ports on the connectivity card, each of the plurality of PCIe connectors capable of carrying PCIe traffic. The connectivity card also includes a PCIe switch circuit configured to communicatively couple the plurality of connectors to a shared connectivity interface carried over a host connector of the connectivity card. The connectivity card further includes control circuitry configured to monitor for connectivity issues that arise with regard to the plurality of PCIe connectors, and responsively mitigate the connectivity issues by at least reconfiguring a communication pathway in the PCIe switch circuit for at least a portion of the PCIe traffic affected by the connectivity issues.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a disaggregated computing architecture is presented. The method includes, receiving user commands to establish compute units among a plurality of physical computing components, each of the compute units comprising one or more of the plurality of physical computing components selected from among central processing units (CPUs), graphics processing units (GPUs), storage modules, and network interface modules. The method also includes forming the compute units based at least on logical partitioning within a Peripheral Component Interconnect Express (PCIe) fabric communicatively coupling the plurality of physical computing components, wherein each of the compute units have visibility over the PCIe fabric to the one or more of the plurality of physical computing components assigned to the associated compute units using the logical partitioning within the PCIe fabric.

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, a computing system is provided. The computing system includes a management processor configured to initiate a peer-to-peer arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device over a PCIe fabric comprising one or more PCIe switches. The peer-to-peer arrangement is established to detect data transfers from the first PCIe device directed to addresses corresponding to an address range established for the second PCIe device by a peer-to-peer management entity executed on a host processor, and redirect the data transfers over the PCIe fabric to the second PCIe device such that the data transfers are received by the second PCIe device without passing through the host processor.

Abstract: Various computer peripheral cards, devices, systems, methods, and software are provided herein. In one example, a storage apparatus includes a plurality of storage device connectors in a stacked arrangement, each configured to mate with associated storage devices and carry Peripheral Component Interconnect Express (PCIe) signaling for the associated storage devices. The storage apparatus also includes a PCIe switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage apparatus, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage apparatus and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.

Abstract: A storage card insertable into a host system is provided that includes a plurality of storage devices connectors. The storage card include slot offset features to offset a circuit board of the storage card from a host system slot alignment. This offset provides for storage device connector placement on both sides of the storage card. The storage card also can include a Peripheral Component Interconnect Express (PCIe) switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage card, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage card and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.

Abstract: A data storage sled is provided. The data storage sled includes a circuit card assembly comprising a plurality of drive connectors for coupling to drive module modules and a host connector for coupling the data storage sled to an external connector, wherein at least a portion of the drive connectors are configured to mount a set of drive modules aligned lengthwise along the circuit card assembly. The data storage sled also includes drive module mounting assembles configured to hold individual ones of the drive modules into associated drive connectors by at least including mounting features to accommodate lengths of the individual ones of the drive modules.

Abstract: Systems, methods, apparatuses, and architectures for storage interposers are provided herein. In one example, an apparatus includes a host connector configured to couple to one or more host systems over associated host Peripheral Component Interconnect Express (PCIe) interfaces, and PCIe switch circuitry configured to receive storage operations over the host connector that are issued by the one or more host systems. The PCIe switch circuitry is configured to monitor when ones of the storage operations correspond to an address range and responsively indicate the ones of the storage operations to a control module. The control module is configured to selectively direct delivery of the ones of the storage operations to corresponding storage areas among one or more storage devices based at least on addressing information monitored for the ones of the storage operations in the PCIe switch circuitry.

Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage system is provided that includes a plurality of storage drives each comprising a Peripheral Component Interconnect Express (PCIe) interface, and configured to store data and retrieve the data stored on associated storage media responsive to storage operations. The data storage system includes one or more processing modules comprising one or more processors communicatively coupled to the plurality of storage drives over a PCIe fabric comprised of one or more PCIe switches. The processors are configured to share a PCIe address space associated with the PCIe fabric for transfer of the storage operations to appropriate ones of the processors that manage ones of the plurality of storage drives.

Abstract: Data storage systems are provided that include network interfaces each configured to receive storage operations issued by one or more host systems for handling by the data storage system, and transfer the storage operations over a Peripheral Component Interconnect Express (PCIe) fabric. The data storage systems also include processors configured to receive the storage operations over the PCIe fabric, process properties of the storage operations against allocation information of a shared PCIe address space to determine target processors to handle the storage operations, and selectively transfer ones of the storage operations to the target processors for handling of the storage operations with associated storage drives coupled over the PCIe fabric. The data storage systems also identifie failed ones of the processors and responsively initiate backup ones of the processors to handle portions of the shared PCIe address space handled by the failed ones of the processors.

Abstract: Various computer peripheral cards, devices, systems, methods, and software are provided herein. In one example, a storage card insertable into a host system includes a plurality of storage device connectors in a stacked arrangement, each configured to mate with associated storage devices and carry Peripheral Component Interconnect Express (PCIe) signaling for the associated storage devices. The storage card also includes a PCIe switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage card, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage card and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.

Abstract: Various computer peripheral cards, devices, systems, methods, and software are provided herein. In one example, a storage card insertable into a connector of a host system includes a plurality of M.2 device connectors in a stacked arrangement comprising a first horizontal row of one or more M.2 device connectors positioned vertically higher in the stacked arrangement than a second horizontal row of one or more M.2 device connectors, the plurality of M.2 device connectors each configured to mate with associated M.2 devices. The storage card also includes a Peripheral Component Interconnect Express (PCIe) switch circuit configured to communicatively couple the plurality of M.2 device connectors and a connector of the storage card, wherein the PCIe switch circuit is configured to receive storage operations over the connector of the storage card and transfer the storage operations for delivery to ones of the plurality of M.2 device connectors over associated PCIe interfaces.