Abstract: The disclosure presents techniques for merging multiple data flows in a network such as a Passive Optical Network (PON). The PON comprises an interface module and network nodes connected to the interface module via an optical fiber link. Each network node further serves client devices. The client devices request multiple data flows, requiring the interface module to serve multiple data flows to a network node for delivery to the devices. The interface module merges received data flows to permit multiple flows to be processed by a single segmentation and reassembly (SAR) engine, reducing hardware cost and complexity within the node. However, subunits associated with different data flows within a merged data flow are not interleaved with one another. Instead, the subunits associated with an original unit of information are transmitted contiguously within the merged data flow, facilitating identification and reassembly of the subunits for a particular microflow.

Abstract: An inverse assembler and converter acquire binary code during inverse assembly of compiled programming code for a software application. A memory image file is generated during compiling of the programming code and a converter is used to trigger a physical address in a memory bus via a logic analyzer. A triggered logical address in the compiled programming code is determined. The triggered logical address is input into the converter. Trigger commands are provided to the logic analyzer that are used to trigger a physical address where binary code is stored in memory. The trigger commands are supplied to the logic analyzer and the memory bus is triggered. The physical address is acquired and converted into a logical address. The memory image file is searched for the logical address. The binary code is acquired from the memory image file at the logical address. The binary code corresponds to only machine code instructions performed during execution of the software application.

Abstract: In general, the present invention is a system and method for interfacing signals with processing elements, such as microprocessors. The present invention utilizes a processing element, an electrical connection, a resistive device, a current sink, a first diode, a second diode, and a buffer. The electrical connection is coupled to the processing element, which is associated with an operating voltage. The resistive device is coupled to the electrical connection, and the first diode is coupled to the electrical connection and the current sink. An anode end of the first diode is coupled to the electrical connection between the resistive device and the processing element, and a cathode end of the first diode is coupled to the current sink. The buffer is coupled to the processing element, which transmits a voltage corresponding with the operating voltage of the processing element to the buffer. The second diode couples the buffer to the current sink.