Patents by Inventor Chrystelle Lagahe

Chrystelle Lagahe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200161172
    Abstract: The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device layer; and alignment marks; b) providing a donor substrate; c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer; d) assembling the donor substrate and the carrier substrate; and e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer; wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Inventors: Marcel Broekaart, Ionut Radu, Chrystelle Lagahe Blanchard
  • Patent number: 9728458
    Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 8, 2017
    Assignee: Soitec
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 9511996
    Abstract: Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 6, 2016
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 9481566
    Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: November 1, 2016
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Publication number: 20160197006
    Abstract: The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device layer; and alignment marks; b) providing a donor substrate; c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer; d) assembling the donor substrate and the carrier substrate; and e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer; wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.
    Type: Application
    Filed: June 24, 2014
    Publication date: July 7, 2016
    Inventors: Marcel Broekaart, Ionut Radu, Chrystelle Lagahe Blanchard
  • Publication number: 20150210540
    Abstract: Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.
    Type: Application
    Filed: July 8, 2013
    Publication date: July 30, 2015
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Publication number: 20150191344
    Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.
    Type: Application
    Filed: July 8, 2013
    Publication date: July 9, 2015
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Publication number: 20150179520
    Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
    Type: Application
    Filed: July 8, 2013
    Publication date: June 25, 2015
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 8927320
    Abstract: A method of bonding by molecular bonding between at least one lower wafer and an upper wafer comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force is applied to a peripheral side of at least one of the two wafers in order to initiate a bonding wave between the two wafers.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: January 6, 2015
    Assignee: Soitec
    Inventors: Chrystelle Lagahe Blanchard, Marcel Broekaart, Arnaud Castex
  • Patent number: 8722515
    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: May 13, 2014
    Assignee: Soitec
    Inventors: Chrystelle Lagahe, Bernard Aspar
  • Patent number: 8628674
    Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: January 14, 2014
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, Soitec
    Inventors: Marc Zussy, Bernard Aspar, Chrystelle Lagahe-Blanchard, Hubert Moriceau
  • Publication number: 20130323861
    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.
    Type: Application
    Filed: August 2, 2013
    Publication date: December 5, 2013
    Applicant: Soitec
    Inventors: Chrystelle Lagahe, Bernard Aspar
  • Patent number: 8530334
    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: September 10, 2013
    Assignee: Soitec
    Inventors: Chrystelle Lagahe, Bernard Aspar
  • Patent number: 8505197
    Abstract: A method of fabricating a multilayer substrate may include bonding a front face of a donor substrate to a front face of a receiver substrate by molecular adhesion to form a stack and applying a heat treatment to the stack to consolidate a bond interface between the donor substrate and the receiver substrate. The method may further include thinning a back face of the donor substrate, trimming a periphery of the donor substrate and at least a portion of a periphery of the receiver substrate, and etching the back face of the donor substrate, the periphery of the donor substrate, and the at least a portion of the periphery of the receiver substrate subsequent to thinning the back face of the donor substrate and trimming the periphery of the donor substrate and the at least a portion of the periphery of the receiver substrate.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: August 13, 2013
    Assignee: Soitec
    Inventor: Chrystelle Lagahe Blanchard
  • Patent number: 8475693
    Abstract: This invention provides composite semiconductor substrates and methods for fabricating such substrates. The composite structures include a semiconductor substrate, a semiconductor superstrate and an intermediate layer interposed between the substrate and the superstrate that comprises a material that undergoes a structural transformation when subject to a suitable heat treatment. The methods provide such a heat treatment so that the intermediate layer becomes spongy or porous, being filled with numerous micro-bubbles or micro-cavities containing a gaseous phase. The composite semiconductor substrates with structurally-transformed intermediate layers have numerous applications.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 2, 2013
    Assignee: Soitec
    Inventors: Michel Bruel, Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Patent number: 8329048
    Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: December 11, 2012
    Assignees: Commissariat a l'Energie Atomique, S.O.I. TEC Silicon On Insulator Technologies of Chemin des Franques
    Inventors: Marc Zussy, Bernard Aspar, Chrystelle Lagahe-Blanchard, Hubert Moriceau
  • Patent number: 8268703
    Abstract: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material and a part of the substrate. Additionally, the surface of the oxidized material may be prepared and the surface may be assembled with a second substrate.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: September 18, 2012
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie
  • Publication number: 20120164778
    Abstract: A method of bonding by molecular bonding between at least one lower wafer and an upper wafer comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force is applied to the peripheral side of at least one of the two wafers in order to initiate a bonding wave between the two wafers.
    Type: Application
    Filed: June 11, 2010
    Publication date: June 28, 2012
    Applicant: SOITEC
    Inventors: Chrystelle Lagahe Blanchard, Marcel Broekaart, Arnaud Castex
  • Patent number: 8158487
    Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: April 17, 2012
    Assignee: Soitec
    Inventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
  • Patent number: 8044465
    Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: October 25, 2011
    Assignee: S.O.I.TEC Solicon On Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe-Blanchard