Patents by Inventor Chrystelle Lagahe

Chrystelle Lagahe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070200144
    Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 30, 2007
    Applicant: TRACIT TECHNOLOGIES
    Inventors: Bernard ASPAR, Chrystelle Lagahe-Blanchard
  • Patent number: 7238598
    Abstract: A method for forming a semiconductor substrate that can be dismantled, comprising the following steps: introduction of gaseous species in the substrate according to conditions enabling the constitution of an embrittled layer by the presence in said layer of micro-cavities and/or micro-bubbles, a thin layer of semiconductor material thus being delimited between the embrittled layer and one face of the substrate, thermal treatment of the substrate to increase the brittleness level of the embrittled layer, said thermal treatment being continued until the appearance of local deformations on said face of the substrate in the form of blisters but without generating exfoliations of the thin layer during this step and during the continuation of the method, epitaxy of semiconductor material on said face of the substrate to provide at least one epitaxial layer on said thin film.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: July 3, 2007
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Chrystelle Lagahe, Bernard Aspar, Aurélie Beaumont
  • Publication number: 20070122926
    Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member maintains the position of the substrate on a moveable support. A cutting mechanism having at least one blade is provided for contacting the substrate and inducing a cleaving wave therein. The cutting mechanism is operatively associated with the positioning member so that the as at least one blade contacts the annular notch, the positioning member prevents movement of the substrate and the moveable support moves away from the substrate to allow the cleaving wave to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.
    Type: Application
    Filed: January 30, 2007
    Publication date: May 31, 2007
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cecile Berne, Olivier Rayssac
  • Publication number: 20070072393
    Abstract: A method for assembling a first and a second wafer of material, including routing at least the first wafer and assembling the first and second wafer.
    Type: Application
    Filed: October 14, 2004
    Publication date: March 29, 2007
    Applicant: TRACIT TECHNOLOGIES
    Inventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Patent number: 7189304
    Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The cutting device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch that is located below the weakened area. The positioning member maintains a predetermined position of the substrate on a support. The device also includes cutting means having at least one blade for contacting the substrate and for inducing a cleaving wave into the substrate. The cutting means is operatively associated with the positioning member so that the at least one blade contacts the annular notch and the positioning member prevents movement of the substrate. The at least one blade induces a cleaving wave of sufficient intensity to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: March 13, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cécile Berne, Olivier Rayssac
  • Publication number: 20070020895
    Abstract: The invention relates to a process for obtaining a thin layer made of a first material on a substrate made of a second material called the final substrate, including the following steps: bonding a thick layer of a first material on one of its main faces on the final substrate at an interface, implantation of gaseous species in the thick layer of first material to create a weakened zone delimiting said thin layer between the interface and the weakened zone, deposit a layer of third material called the self-supporting layer on the thick layer made of first material, fracture within the structure composed of the final substrate, the thick layer of first material and the layer of third material, at the weakened zone to supply the substrate supporting said thin layer.
    Type: Application
    Filed: June 3, 2004
    Publication date: January 25, 2007
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Hubert Moriceau, Chrystelle Lagahe, Benoit Bataillou
  • Publication number: 20060019476
    Abstract: The invention concerns a method for forming a semiconductor substrate that can be dismantled, comprising the following steps: introduction of gaseous species in the substrate (1) according to conditions enabling the constitution of an embrittled layer by the presence in said layer of micro-cavities and/or micro-bubbles, a thin layer of semiconductor material thus being delimited between the embrittled layer and one face (2) of the substrate, thermal treatment of the substrate to increase the brittleness level of the embrittled layer, said thermal treatment being continued until the appearance of local deformations on said face (2) of the substrate (1) in the form of blisters but without generating exfoliations of the thin layer during this step and during the continuation of the method, epitaxy of semiconductor material (6) on said face of the substrate to provide at least one epitaxial layer on said thin film.
    Type: Application
    Filed: October 3, 2003
    Publication date: January 26, 2006
    Inventors: Chrystelle Lagahe, Bernard Aspar, Aurelie Beaumont
  • Patent number: 6936523
    Abstract: The present invention relates to a method for manufacturing a heterogeneous material structure. The method includes forming a predetermined detachment area in a source substrate, and bonding the source substrate to a handle substrate to form a source-handle structure. The source-handle-structure is then annealed at a first energy level that is lower than the energy of a thermal detachment budget and stopping before detachment of the source substrate. Lastly, the source-handle-structure is annealed at a second energy level that is lower than the first energy level at least until the substrate detaches at the predetermined detachment area.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: August 30, 2005
    Assignees: S.O.I.Tec Silicon on Insulator Technologies S.A., Commisariat à l'énergie Atomique (CEA)
    Inventors: Cecile Berne, Bruno Ghyselen, Chrystelle Lagahe, Thibaut Maurice
  • Publication number: 20040161904
    Abstract: The present invention relates to a method for manufacturing a heterogeneous material structure. The method includes forming a predetermined detachment area in a source substrate, and bonding the source substrate to a handle substrate to form a source-handle structure. The source-handle-structure is then annealed at a first energy level that is lower than the energy of a thermal detachment budget and stopping before detachment of the source substrate. Lastly, the source-handle-structure is annealed at a second energy level that is lower than the first energy level at least until the substrate detaches at the predetermined detachment area.
    Type: Application
    Filed: December 10, 2003
    Publication date: August 19, 2004
    Applicant: SOITEC & CEA
    Inventors: Cecile Berne, Bruno Ghyselen, Chrystelle Lagahe, Thibaut Maurice
  • Publication number: 20040144487
    Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The cutting device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch that is located below the weakened area. The positioning member maintains a predetermined position of the substrate on a support. The device also includes cutting means having at least one blade for contacting the substrate and for inducing a cleaving wave into the substrate. The cutting means is operatively associated with the positioning member so that the at least one blade contacts the annular notch and the positioning member prevents movement of the substrate. The at least one blade induces a cleaving wave of sufficient intensity to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.
    Type: Application
    Filed: October 7, 2003
    Publication date: July 29, 2004
    Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cecile Berne, Olivier Rayssac
  • Publication number: 20030077885
    Abstract: This invention relates to a substrate (1) weakened by the presence of a micro-cavities zone, the micro-cavities zone (4′) delimiting a thin layer (5) with one face (2) of the substrate (1), some or all of the gaseous species having been eliminated from the micro-cavities (4′).
    Type: Application
    Filed: November 22, 2002
    Publication date: April 24, 2003
    Inventors: Bernard Aspar, Chrystelle Lagahe, Olivier Rayssac, Bruno Ghyselen
  • Patent number: 6465327
    Abstract: The invention relates to a method for producing a thin membrane, comprising the following steps: implanting gas species, through one surface of a first substrate (10) and through one surface of a second substrate (20), which in said substrates are able to create microcavities (11, 21) delimiting, for each substrate, a thin layer (13, 23) lying between these microcavities and the implanted surface, the microcavities being able, after their implantation, to cause detachment of the thin layer from its substrate; assembly of the first substrate (10) onto the second substrate (20) such that their implanted surfaces face one another; detaching each thin layer (13, 23) from its substrate (10, 20), the thin layers remaining assembled together to form said thin membrane. The invention also concerns a thin membrane structure obtained with this method.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: October 15, 2002
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bernard Aspar, Michel Bruel, Claude Jaussaud, Chrystelle Lagahe