Patents by Inventor Chrystelle Lagahe

Chrystelle Lagahe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110250416
    Abstract: This invention provides composite semiconductor substrates and methods for fabricating such substrates. The composite structures include a semiconductor substrate, a semiconductor superstrate and an intermediate layer interposed between the substrate and the superstrate that comprises a material that undergoes a structural transformation When subject to a suitable heat treatment. The methods provide such a heat treatment so that the intermediate layer becomes spongy or porous, being filled with numerous micro-bubbles or micro-cavities containing a gaseous phase. The composite semiconductor substrates with structurally-transformed intermediate layers have numerous applications.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 13, 2011
    Inventors: Michel Bruel, Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Publication number: 20110233719
    Abstract: The invention relates to a test method comprising an electrical connection contact on the support of a substrate of the semiconductor-on-insulator type. This method is remarkable in that it comprises the steps of: a) taking a substrate of the semiconductor-on-insulator type comprising a support substrate entirely covered with an insulator layer and an active layer, a portion of the insulator layer being buried between the active layer and the front face of the support substrate, b) removing a portion of the insulator layer that extends at the periphery of the front face of the support substrate and/or that extends on its rear face, so as to delimit at least one insulator-free accessible area of the support substrate, while retaining at least one portion of the insulator layer on the rear face, c) applying an electrical voltage to the accessible area in order to make the electrical connection contact.
    Type: Application
    Filed: January 14, 2010
    Publication date: September 29, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Chrystelle Lagahe Blanchard
  • Publication number: 20110183495
    Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 28, 2011
    Inventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
  • Patent number: 7927980
    Abstract: The invention concerns a method for forming a growth mask on the surface of an initial crystalline substrate, comprising the following steps: formation of a layer of second material on one of the faces of the initial substrate of first material, formation of a pattern in the thickness of the layer of second material so as to expose the zones of said face of the initial substrate, said zones forming growth windows on the initial substrate, the method being characterized in that the formation of the pattern is obtained by ion implantation carried out in the surface layer of the initial substrate underlying the layer of second material, the implantation conditions being such that they cause, directly or after a heat treatment, on said face of the initial substrate, the appearance of exfoliated zones of first material leading to the localized removal of the zones of second material covering the exfoliated zones of first material, thereby locally exposing the initial substrate and forming growth windows on
    Type: Grant
    Filed: November 25, 2005
    Date of Patent: April 19, 2011
    Assignee: COMMISSARIAT a l'Energie Atomique
    Inventors: Aurélie Tauzin, Chrystelle Lagahe-Blanchard
  • Publication number: 20110076849
    Abstract: A method of fabricating a multilayer substrate may include bonding a front face of a donor substrate to a front face of a receiver substrate by molecular adhesion to form a stack and applying a heat treatment to the stack to consolidate a bond interface between the donor substrate and the receiver substrate. The method may further include thinning a back face of the donor substrate, trimming a periphery of the donor substrate and at least a portion of a periphery of the receiver substrate, and etching the back face of the donor substrate, the periphery of the donor substrate, and the at least a portion of the periphery of the receiver substrate subsequent to thinning the back face of the donor substrate and trimming the periphery of the donor substrate and the at least a portion of the periphery of the receiver substrate.
    Type: Application
    Filed: August 5, 2010
    Publication date: March 31, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Chrystelle Lagahe Blanchard
  • Publication number: 20100285213
    Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.
    Type: Application
    Filed: January 16, 2009
    Publication date: November 11, 2010
    Inventors: Chrystelle Lagahe, Bernard Aspar
  • Patent number: 7807482
    Abstract: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: October 5, 2010
    Assignee: S.O.I.Tec Silicon On Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Patent number: 7807548
    Abstract: The invention provides a method for forming a semiconductor component with a rough buried interface. The method includes providing a first semiconductor substrate having a first surface of roughness R1. The method further includes thermally oxidizing the first surface of the first semiconductor substrate to form an oxide layer defining an external oxide surface on the first semiconductor substrate and a buried oxide-semiconductor interface below the oxide surface, so that the buried oxide surface has a roughness R2 that is less than R1. The method also includes assembling the oxide surface of the first semiconductor substrate with a second substrate. The invention also provides a component formed according to the method of the invention.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: October 5, 2010
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie
  • Patent number: 7776714
    Abstract: The invention relates to a process for obtaining a thin layer made of a first material on a substrate made of a second material called the final substrate, including the following steps: bonding a thick layer of a first material on one of its main faces on the final substrate at an interface, implantation of gaseous species in the thick layer of first material to create a weakened zone delimiting said thin layer between the interface and the weakened zone, deposit a layer of third material called the self-supporting layer on the thick layer made of first material, fracture within the structure composed of the final substrate, the thick layer of first material and the layer of third material, at the weakened zone to supply the substrate supporting said thin layer.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: August 17, 2010
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Hubert Moriceau, Chrystelle Lagahe, Benoit Bataillou
  • Publication number: 20100176397
    Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 15, 2010
    Applicant: TRACIT TECHNOLOGIES
    Inventors: Bernard ASPAR, Chrystelle LAGAHE-BLANCHARD
  • Patent number: 7709305
    Abstract: The invention relates to a method for producing a semiconductor structure comprising a superficial layer, at least one embedded layer, and a support, which method comprises: a step of forming, on a first support, patterns in a first material, a step of forming a semiconductor layer, between and on said patterns, a step of assembling said semiconductor layer with a second support.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Tracit Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Publication number: 20100032085
    Abstract: The disclosure relates to methods and systems for separating a membrane from a substrate. In accordance with a preferred embodiment, the method includes applying at least one member to the membrane by way of an adhesive, wherein the adhesive is applied to substantially less than the entirety of the surface of said membrane which is not facing the substrate. The method further includes separating at least a part of the membrane from the substrate by applying a force to the at least one member.
    Type: Application
    Filed: September 22, 2009
    Publication date: February 11, 2010
    Inventors: Nicolas Sousbie, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Publication number: 20090301995
    Abstract: Process for fabricating a structure in the form of a wafer, including at least a substrate, a superstrate and at least one intermediate layer interposed between the substrate and the superstrate, the process including: forming, on a substrate, at least one intermediate layer including at least one base material in which extrinsic atoms or molecules are distributed, these differing from the atoms or molecules of the base material, so as to constitute a substructure; applying a base heat treatment to this substructure such that, in the temperature range of this heat treatment, the presence of the chosen extrinsic atoms or molecules in the chosen base material causes a structural transformation of said intermediate layer; and joining a superstrate to said heat-treated intermediate layer so as to obtain said structure in the form of a wafer.
    Type: Application
    Filed: December 27, 2006
    Publication date: December 10, 2009
    Applicant: Tracit Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Publication number: 20090149005
    Abstract: The invention concerns a method for forming a growth mask on the surface of an initial crystalline substrate, comprising the following steps: formation of a layer of second material on one of the faces of the initial substrate of first material, formation of a pattern in the thickness of the layer of second material so as to expose the zones of said face of the initial substrate, said zones forming growth windows on the initial substrate, the method being characterised in that the formation of the pattern is obtained by ion implantation carried out in the surface layer of the initial substrate underlying the layer of second material, the implantation conditions being such that they cause, directly or after a heat treatment, on said face of the initial substrate, the appearance of exfoliated zones of first material leading to the localised removal of the zones of second material covering the exfoliated zones of first material, thereby locally exposing the initial substrate and forming growth windows on the
    Type: Application
    Filed: November 25, 2005
    Publication date: June 11, 2009
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Aurelie Tauzin, Chrystelle Lagahe-Blanchard
  • Publication number: 20090095399
    Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.
    Type: Application
    Filed: December 22, 2005
    Publication date: April 16, 2009
    Applicants: Commissariat A L'Energie Atomique, Tracit Technologies
    Inventors: Marc Zussy, Bernard Aspar, Chrystelle Lagahe-Blanchard, Hubert Moriceau
  • Patent number: 7498245
    Abstract: This invention relates to a substrate (1) weakened by the presence of a micro-cavities zone, the micro-cavities zone (4?) delimiting a thin layer (5) with one face (2) of the substrate (1), some or all of the gaseous species having been eliminated from the micro-cavities (4?). The invention also relates to a process for the production of such a substrate.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: March 3, 2009
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Bernard Aspar, Chrystelle Lagahe, Olivier Rayssac, Bruno Ghyselen
  • Publication number: 20080254596
    Abstract: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.
    Type: Application
    Filed: June 2, 2005
    Publication date: October 16, 2008
    Applicant: TRACIT TECHNOLOGIES
    Inventors: Bernard Aspar, Chrystelle Lagahe-Blanchard
  • Patent number: 7406994
    Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member maintains the position of the substrate on a moveable support. A cutting mechanism having at least one blade is provided for contacting the substrate and inducing a cleaving wave therein. The cutting mechanism is operatively associated with the positioning member so that the as at least one blade contacts the annular notch, the positioning member prevents movement of the substrate and the moveable support moves away from the substrate to allow the cleaving wave to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: August 5, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cécile Berne, Olivier Rayssac
  • Publication number: 20080176382
    Abstract: The invention provides a method for forming a semiconductor component with a rough buried interface. The method includes providing a first semiconductor substrate having a first surface of roughness R1. The method further includes thermally oxidizing the first surface of the first semiconductor substrate to form an oxide layer defining an external oxide surface on the first semiconductor substrate and a buried oxide-semiconductor interface below the oxide surface, so that the buried oxide surface has a roughness R2 that is less than R1. The method also includes assembling the oxide surface of the first semiconductor substrate with a second substrate. The invention also provides a component formed according to the method of the invention.
    Type: Application
    Filed: July 13, 2007
    Publication date: July 24, 2008
    Applicant: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie
  • Publication number: 20080176381
    Abstract: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material and a part of the substrate. Additionally, the surface of the oxidized material may be prepared and the surface may be assembled with a second substrate.
    Type: Application
    Filed: July 13, 2007
    Publication date: July 24, 2008
    Applicant: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie