Patents by Inventor Chu-Chung Lee
Chu-Chung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8907485Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.Type: GrantFiled: August 24, 2012Date of Patent: December 9, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Leo M. Higgins, III, Chu-Chung Lee
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Publication number: 20140308779Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: ApplicationFiled: June 26, 2014Publication date: October 16, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Chu-Chung LEE, Kian Leong CHIN, Kevin J. HESS, Patrick P. JOHNSTON, Tu-Anh N. TRAN, Heng Keong YIP
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Patent number: 8853867Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.Type: GrantFiled: January 31, 2014Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Sheila F. Chopin, Varughese Mathew, Leo M. Higgins, III, Chu-Chung Lee
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Patent number: 8791582Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: GrantFiled: July 28, 2010Date of Patent: July 29, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Chu-Chung Lee, Kian Leong Chin, Kevin J. Hess, Patrick Johnston, Tu-Anh N. Tran, Heng Keong Yip
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Publication number: 20140145339Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.Type: ApplicationFiled: January 31, 2014Publication date: May 29, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Sheila F. CHOPIN, Varughese MATHEW, Leo M. HIGGINS, III, Chu-Chung LEE
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Publication number: 20140061910Abstract: A method of making a semiconductor device can comprise forming a copper bond pad on an integrated circuit device; forming a first passivation layer on the integrated circuit device and the copper bond pad; forming a second passivation layer on the first passivation layer; forming a mask over the first and second passivation layers around the copper bond pad; etching the second passivation layer over the copper bond pad; and cleaning the first passivation layer over the copper bond pad. At least a portion of the first passivation layer remains over the copper bond pad after the etching the second passivation layer. A thickness of the first passivation layer over the copper bond pad is selected to protect the copper bond pad from oxidation and to allow wire bonding to the copper bond pad through the first passivation layer.Type: ApplicationFiled: August 31, 2012Publication date: March 6, 2014Inventors: CHU-CHUNG LEE, VIKAS R. SHETH
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Publication number: 20140054781Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Inventors: Leo M. Higgins, III, Chu-Chung Lee
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Patent number: 8643197Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.Type: GrantFiled: October 15, 2012Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Sheila F. Chopin, Varughese Mathew, Leo M. Higgins, III, Chu-Chung Lee
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Publication number: 20130193589Abstract: A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Inventors: ROBERT J. WENZEL, Kevin J. Hess, Chu-Chung Lee
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Patent number: 8318549Abstract: An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.Type: GrantFiled: October 29, 2009Date of Patent: November 27, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Chu-Chung Lee
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Publication number: 20120153464Abstract: Methods of forming gold-aluminum electrical interconnects are described. The method may include interposing a diffusion retardant layer between the gold and the aluminum, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum; forming alloys of gold and the diffusion retardant material in regions containing the material and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material; and forming a continuous electrically conducting path between the aluminum and the gold. A structure for gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad and a diffusion retardant layer in contact with the bond pad, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material.Type: ApplicationFiled: January 23, 2012Publication date: June 21, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Kevin J. Hess, Chu-Chung Lee
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Patent number: 8129226Abstract: A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.Type: GrantFiled: May 10, 2007Date of Patent: March 6, 2012Assignee: Freescale Semiconductor, Inc.Inventors: James P. Johnston, Chu-Chung Lee, Tu-Anh N. Tran, James W. Miller, Kevin J. Hess
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Publication number: 20120025401Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: ApplicationFiled: July 28, 2010Publication date: February 2, 2012Inventors: CHU-CHUNG LEE, Kian Leong Chin, Kevin J. Hess, Patrick Johnston, Tu-Anh N. Tran, Heng Keong Yip
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Patent number: 8105933Abstract: In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum (1002), the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum (1004); forming alloys of gold and the diffusion retardant material in regions containing the material (1006) and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material (1008); and forming a continuous electrically conducting path between the aluminum and the gold (1010). In some embodiments, a structure useful in a gold-aluminum interconnect is provided.Type: GrantFiled: January 31, 2007Date of Patent: January 31, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Chu-Chung Lee
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Publication number: 20110101517Abstract: An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.Type: ApplicationFiled: October 29, 2009Publication date: May 5, 2011Inventors: Kevin J. Hess, Chu-Chung Lee
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Patent number: 7829997Abstract: A semiconductor device (601) is provided which comprises a substrate (603); a semiconductor device (605) disposed on said substrate and having a first major surface; a first metal strap (615) which is in electrical contact with said substrate and which is adapted to provide power to a first region (608) of said semiconductor device; and a second metal strap (616) which is in electrical contact with said substrate and which is adapted to provide ground to a second region (609) of said semiconductor device.Type: GrantFiled: April 4, 2007Date of Patent: November 9, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Chu-Chung Lee, James W. Miller
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Publication number: 20100270663Abstract: A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.Type: ApplicationFiled: May 10, 2007Publication date: October 28, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: James P. Johnston, Chu-Chung Lee, Tu-Anh N. Tran, James W. Miller, Kevin J. Hess
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Patent number: 7821104Abstract: A package device has a package substrate, a semiconductor die on the package substrate, and a molding compound on the package substrate and over the semiconductor die. The semiconductor die has a last passivation layer, an active circuit region in an internal portion of the die, an edge seal region along a periphery of the die, and a structure over the edge seal region extending above the last passivation layer, covered by the molding compound, and comprising a polymer material. The structure may extend at least five microns above the last passivation layer. The structure stops cracks in the molding compound from reaching the active circuit region. The cracks, if not stopped, can reach wire bonds in the active region and cause them to fail.Type: GrantFiled: August 29, 2008Date of Patent: October 26, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Chu-Chung Lee, Min Ding, Kevin J. Hess, Peng Su
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Patent number: 7750465Abstract: A packaged integrated circuit has an integrated circuit over a support structure. A plurality of bond wires connected between active terminals of the integrated circuit and the support structure. An encapsulant overlies the support structure, the integrated circuit, and the bond wires. The encapsulant has a first open location in the encapsulant so that a first bond wire is exposed and a second open location in the encapsulant so that a second bond wire is exposed. First and second conductive structures are exposed outside the packaged integrated circuit and are located at the first and second open locations, respectively, and electrically connected to the first and second bond wires, respectively.Type: GrantFiled: February 28, 2007Date of Patent: July 6, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kevin J. Hess, Chu-Chung Lee
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Publication number: 20100052106Abstract: A package device has a package substrate, a semiconductor die on the package substrate, and a molding compound on the package substrate and over the semiconductor die. The semiconductor die has a last passivation layer, an active circuit region in an internal portion of the die, an edge seal region along a periphery of the die, and a structure over the edge seal region extending above the last passivation layer, covered by the molding compound, and comprising a polymer material. The structure may extend at least five microns above the last passivation layer. The structure stops cracks in the molding compound from reaching the active circuit region. The cracks, if not stopped, can reach wire bonds in the active region and cause them to fail.Type: ApplicationFiled: August 29, 2008Publication date: March 4, 2010Inventors: Chu-Chung LEE, Min DING, Kevin J. Hess, Peng SU