Patents by Inventor Chu-Chung Lee

Chu-Chung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6992377
    Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: January 31, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaping Zhou, Chu-Chung Lee
  • Publication number: 20050189643
    Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 1, 2005
    Inventors: Yaping Zhou, Chu-Chung Lee
  • Patent number: 6937047
    Abstract: A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: August 30, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tu-Anh Tran, Richard K. Eguchi, Peter R. Harper, Chu-Chung Lee, William M. Williams, Lois Yong
  • Patent number: 6933614
    Abstract: An integrated circuit die (10) has a copper contact (16, 18), which, upon exposure to the ambient air, forms a native copper oxide. An organic material is applied to the copper contact which reacts with the native copper oxide to form an organic coating (12, 14) on the copper contact in order to prevent further copper oxidation. In this manner, further processing at higher temperatures, such as those greater than 100 degrees Celsius, is not inhibited by excessive copper oxidation. For example, due to the organic coating, the high temperature of the wire bond process does not result in excessive oxidation which would prevent reliable wire bonding. Thus, the formation of the organic coating allows for a reliable and thermal resistance wire bond (32, 34). Alternatively, the organic coating can be formed over exposed copper at any time during the formation of the integrated circuit die to prevent or limit the formation of copper oxidation.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 23, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chu-Chung Lee, Fuaida Harun, Kevin J. Hess, Lan Chu Tan, Cheng Choi Yong
  • Publication number: 20050030055
    Abstract: A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 10, 2005
    Inventors: Tu-Anh Tran, Richard Eguchi, Peter Harper, Chu-Chung Lee, William Williams, Lois Yong
  • Publication number: 20040195696
    Abstract: An integrated circuit die (10) has a copper contact (16, 18), which, upon exposure to the ambient air, forms a native copper oxide. An organic material is applied to the copper contact which reacts with the native copper oxide to form an organic coating (12, 14) on the copper contact in order to prevent further copper oxidation. In this manner, further processing at higher temperatures, such as those greater than 100 degrees Celsius, is not inhibited by excessive copper oxidation. For example, due to the organic coating, the high temperature of the wire bond process does not result in excessive oxidation which would prevent reliable wire bonding. Thus, the formation of the organic coating allows for a reliable and thermal resistance wire bond (32, 34). Alternatively, the organic coating can be formed over exposed copper at any time during the formation of the integrated circuit die to prevent or limit the formation of copper oxidation.
    Type: Application
    Filed: September 15, 2003
    Publication date: October 7, 2004
    Inventors: Chu-Chung Lee, Fuaida Harun, Kevin J. Hess, Lan Chu Tan, Cheng Choi Yong
  • Patent number: 6196002
    Abstract: A package for housing a device (e.g., an integrated circuit chip or die) is disclosed including a ball grid array substrate and a thermoelectric cooler (e.g., a Peltier effect device). The thermoelectric cooler is housed within the package. The thermoelectric cooler is coupled to the ball grid array substrate and includes a hotter portion and a cooler portion in response to an electric potential difference. The thermoelectric cooler receives the electric potential difference from the package.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: March 6, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Newman, Chu-Chung Lee